IDT74LVCH16374APVG INTEGRATED DEVICE TECHNOLOGY, IDT74LVCH16374APVG Datasheet

IDT74LVCH16374APVG

Manufacturer Part Number

IDT74LVCH16374APVG

Description

74LVCH, SMD, 74LVCH16374, SSOP48

Manufacturer

INTEGRATED DEVICE TECHNOLOGY

Datasheet

1.IDT74LVCH16374APVG.pdf (6 pages)

Specifications of IDT74LVCH16374APVG

Flip-flop Type

Propagation Delay

4.5ns

Frequency

150MHz

Output Current

24mA

Supply Voltage Range

2.7V To 3.6V

Logic Case Style

SSOP

No. Of Pins

Operating

RoHS Compliant

Trigger Type

Positive Edge

Ic Output Type

Tri State

Rohs Compliant

Yes

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FEATURES:

• Typical t

• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using

• V

• CMOS power levels (0.4μ μ μ μ μ W typ. static)

• All inputs, outputs, and I/O are 5V tolerant

• Supports hot insertion

• Available in SSOP and TSSOP packages

DRIVE FEATURES:

• High Output Drivers: ±24mA

• Reduced system switching noise

APPLICATIONS:

• 5V and 3.3V mixed voltage systems

• Data communication and telecommunication systems

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

INDUSTRIAL TEMPERATURE RANGE

FUNCTIONAL BLOCK DIAGRAM

IDT74LVCH16374A

3.3V CMOS 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP

machine model (C = 200pF, R = 0)

CLK

= 3.3V ± 0.3V, Normal Range

= 2.7V to 3.6V, Extended Range

SK(o)

(Output Skew) < 250ps

TO SEVEN OTHER CHANNELS

3.3V CMOS 16-BIT

EDGE-TRIGGERED D-TYPE FLIP-

FLOP WITH 3-STATE OUTPUTS,

5V TOLERANT I/O AND BUS-HOLD

DESCRIPTION

advanced dual metal CMOS technology. This high-speed, low-power

storage. The Output Enable (OE) and clock (CLK) controls are organized

to operate each device as two 8-bit registers or one 16-bit register with

common clock. Flow-through organization of signal pins simplifies layout. All

inputs are designed with hysteresis for improved noise margin.

This feature allows the use of this device as a translator in a mixed 3.3V/5V

supply system.

driver is capable of driving a moderate to heavy load while maintaining

speed performance.

whenever the input goes to a high impedance. This prevents floating inputs

and eliminates the need for pull-up/down resistors.

The LVCH16374A 16-bit edge-triggered D-type register is built using

All pins of the LVCH16374A can be driven from either 3.3V or 5V devices.

The LVCH16374A has been designed with a

The LVCH16374A has “bus-hold” which retains the inputs’ last state

CLK

TO SEVEN OTHER CHANNELS

INDUSTRIAL TEMPERATURE RANGE

IDT74LVCH16374A

24mA output driver. This

MARCH 2006

DSC-4643/4

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IDT74LVCH16374APVG Summary of contents

Page 1

... SEVEN OTHER CHANNELS The IDT logo is a registered trademark of Integrated Device Technology, Inc. INDUSTRIAL TEMPERATURE RANGE © 2006 Integrated Device Technology, Inc. 3.3V CMOS 16-BIT EDGE-TRIGGERED D-TYPE FLIP- FLOP WITH 3-STATE OUTPUTS, 5V TOLERANT I/O AND BUS-HOLD DESCRIPTION The LVCH16374A 16-bit edge-triggered D-type register is built using advanced dual metal CMOS technology ...

Page 2

IDT74LVCH16374A 3.3V CMOS 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP PIN CONFIGURATION GND ...

Page 3

IDT74LVCH16374A 3.3V CMOS 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Following Conditions Apply Unless Otherwise Specified: Operating Condition –40°C to +85°C A Symbol Parameter V Input HIGH Voltage Level IH V Input LOW Voltage Level ...

Page 4

IDT74LVCH16374A 3.3V CMOS 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP OUTPUT DRIVE CHARACTERISTICS Symbol Parameter V Output HIGH Voltage OH V Output LOW Voltage OL NOTE and V must be within the min. or max. range shown in the DC ELECTRICAL ...

Page 5

IDT74LVCH16374A 3.3V CMOS 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP TEST CIRCUITS AND WAVEFORMS TEST CONDITIONS (1) (1) Symbol V = 3.3V±0. 2. LOAD V 2.7 2 1.5 1 300 300 LZ ...

Page 6

IDT74LVCH16374A 3.3V CMOS 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP ORDERING INFORMATION X XX IDT XX LVC Temp. Range Bus-Hold Family CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138 XX XXXX Device Type Package PV PVG PA PAG 374A 16 ...

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