25LC1024-I/ST Microchip Technology, 25LC1024-I/ST Datasheet - Page 10

IC, EEPROM, 1MBIT, SERIAL, 20MHZ TSSOP-8

25LC1024-I/ST

Manufacturer Part Number
25LC1024-I/ST
Description
IC, EEPROM, 1MBIT, SERIAL, 20MHZ TSSOP-8
Manufacturer
Microchip Technology
Datasheet

Specifications of 25LC1024-I/ST

Memory Size
1Mbit
Ic Interface Type
SPI
Clock Frequency
20MHz
Supply Voltage Range
2.5V To 5.5V
Memory Case Style
TSSOP
No. Of Pins
8
Operating Temperature Range
-40°C To +85°C
Memory Configuration
128K X 8
25LC1024
2.3
The 25LC1024 contains a write enable latch. See
Table 2-4 for the Write-Protect Functionality Matrix.
This latch must be set before any write operation will be
completed internally. The WREN instruction will set the
latch, and the WRDI will reset the latch.
FIGURE 2-4:
FIGURE 2-5:
DS22064C-page 10
Write Enable (WREN) and Write
Disable (WRDI)
WRITE ENABLE SEQUENCE (WREN)
WRITE DISABLE SEQUENCE (WRDI)
SCK
CS
SO
SCK
SI
CS
SO
SI
0
0
0
0
0
1
0
1
High-Impedance
0
High-Impedance
0
2
2
0
0
3
3
The following is a list of conditions under which the
write enable latch will be reset:
• Power-up
• WRDI instruction successfully executed
• WRSR instruction successfully executed
• WRITE instruction successfully executed
• PE instruction successfully executed
• SE instruction successfully executed
• CE instruction successfully executed
0
0
4
4
1
5
1
5
1
6
1 0
6
0
7
0
7
© 2008 Microchip Technology Inc.

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