FM25640-G Ramtron, FM25640-G Datasheet - Page 6

• Manufacturer Part Number: FM25640-G
• Description: IC, FRAM, 64KBIT, 5MHZ, SOIC-8
• Manufacturer: Ramtron

Specifications of FM25640-G

• Memory Size: 64Kbit
• Memory Configuration: 8K X 8
• Ic Interface Type: Serial, SPI
• Supply Voltage Range: 4.5V To 5.5V
• Memory Case Style: SOIC
• No. Of Pins: 8
• Operating Temperature Range: -40°C To +85°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

RDSR - Read Status Register
The RDSR command allows the bus master to verify
the contents of the Status register. Reading Status
provides information about the current state of the
write protection features. Following the RDSR op-
code, the FM25640 will return one byte with the
contents of the Status register. The Status register is
described in detail below.
Status Register & Write Protection
The write protection features of the FM25640 are
multi-tiered. First, a WREN op-code must be issued
prior to any write operation. Assuming that writes are
enabled using WREN, writes to memory are
controlled by the Status register. As described above,
writes to the status register are performed using the
WRSR command and subject to the /WP pin. The
Status Register is organized as follows.
Table 2. Status Register
Bits 0 and 4-6 are fixed at 0 and cannot be modified.
Note that bit 0 (Ready in EEPROMs) is unnecessary
as the FRAM writes in real-time and is never busy.
The WPEN, BP1 and BP0 control write protection
features. They are nonvolatile (shaded yellow). The
WEL flag indicates the state of the Write Enable
Rev. 3.2
Feb. 2011
Bit
Name
WPEN
7
6
0
5
0
4
0
BP1
3
BP0
Figure 7. RDSR Bus Configuration
Figure 8. WRSR Bus Configuration
2
WEL
1
0
0
WRSR – Write Status Register
The WRSR command allows the user to select
certain write protection features by writing a byte to
the Status register. Prior to issuing a WRSR
command, the /WP pin must be high or inactive. Note
that on the FM25640, /WP only prevents writing to
the Status register, not the memory array. Prior to
sending the WRSR command, the user must send a
WREN command to enable writes. Note that
executing a WRSR command is a write operation and
therefore clears the Write Enable Latch. The bus
configuration of RDSR and WRSR in the timing
diagrams below.
Latch. This bit is internally set by the WREN
command and is cleared by terminating a write cycle
(/CS high) or by using the WRDI command.
BP1 and BP0 are memory block write protection bits.
They specify portions of memory that are write-
protected as shown in the following table.
Table 3. Block Memory Write Protection
BP1
0
0
1
1
BP0
0
1
0
1
Protected Address Range
None
1800h to 1FFFh (upper ¼)
1000h to 1FFFh (upper ½)
0000h to 1FFFh (all)
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