PIC32MX440F128L-80I/BG Microchip Technology, PIC32MX440F128L-80I/BG Datasheet - Page 16

• Manufacturer Part Number: PIC32MX440F128L-80I/BG
• Description: IC, 32BIT MCU, PIC32, 80MHZ, BGA-100
• Manufacturer: Microchip Technology
• Series: PIC® 32MXr

Specifications of PIC32MX440F128L-80I/BG

• Controller Family/series: PIC32
• Ram Memory Size: 32KB
• Cpu Speed: 80MHz
• No. Of Timers: 5
• Interface: EUSART, I2C, SPI, USB
• No. Of Pwm Channels: 5
• Core Size: 32 Bit
• Program Memory Size: 128 KB
• Core Processor: MIPS32® M4K™
• Speed: 80MHz
• Connectivity: I²C, IrDA, LIN, PMP, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 121-TFBGA
• Embedded Interface Type: EUSART, I2C, SPI, USB
• Rohs Compliant: Yes
• Processor Series: PIC32MX4xx
• Core: MIPS
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: EUART, I2C, SPI
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 85
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, DM320003, DM320002, MA320002
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 876-1000 - PIC32 BREAKOUT BOARD
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

PIC32MX3XX/4XX
58. Module: SPI
59. Module: UART
60. Module: UART
DS80440D-page 16
In Slave mode when entering Sleep mode after a
SPI transfer with SPI interrupts enabled, a false
interrupt may be generated waking the device.
This interrupt can be cleared; however, entering
Sleep may cause the condition to occur again.
Work around
Do not use SPI in Slave mode as a wake-up
source from Sleep.
Affected Silicon Revisions
In IrDA
UART TX data is corrupted when the BRG value is
greater than 0x200.
Work around
Use the Peripheral Bus (PB) divisor to lower the
PB frequency such that the required UART BRG
value is less than 0x201.
Affected Silicon Revisions
The UART module is not fully IrDA compliant. The
module does not detect the 1.6 µs minimum bit
width at all baud rates as defined in the IrDA spec-
ification. The module does detect the 3/16 bit width
at all baud rates.
Work around
None.
Affected Silicon Revisions
B2
B2
B2
X
X
X
®
B3
B3
B3
X
X
X
mode with baud clock output enabled, the
B4
B4
B4
X
X
X
B6
B6
B6
X
X
X
61. Module: RTCC
62. Module: PORTS
63. Module: UART
The
ALRMTIME and ALRMDATE) are reset by any
device Reset.
Work around
For devices with code-protect disabled: If the
alarm information must be retained through a
Reset, the information must be stored in RAM or
Flash.
Affected Silicon Revisions
When an I/O pin is set to output a logic high signal,
and is then changed to an input using the TRISx
registers, the I/O pin should immediately tri-state
and let the pin float. Instead, the pin will continue
to partially drive a logic high signal out for a period
of time.
Work around
The pin should be driven low prior to being tri-stated
if it is desirable for the pin to tri-state quickly.
Affected Silicon Revisions
The OERR bit does not get cleared on a module
reset. If the OERR bit is set and the module is dis-
abled, the OERR bit retains its status even after
the UART module is reinitialized.
Work around
The user software must check this bit in the UART
module initialization routine and clear it if it is set.
Affected Silicon Revisions
B2
B2
B2
X
X
X
RTCC
B3
B3
B3
X
X
X
B4
B4
B4
X
X
X
alarm
© 2010 Microchip Technology Inc.
B6
B6
B6
X
X
X
registers
(RTCALRM,