PIC32MX695F512L-80I/BG Microchip Technology, PIC32MX695F512L-80I/BG Datasheet - Page 6

• Manufacturer Part Number: PIC32MX695F512L-80I/BG
• Description: IC, 32BIT MCU, PIC32, 80MHZ, BGA-100
• Manufacturer: Microchip Technology
• Series: PIC® 32MXr

Specifications of PIC32MX695F512L-80I/BG

• Controller Family/series: PIC32
• Ram Memory Size: 128KB
• Cpu Speed: 80MHz
• No. Of Timers: 5
• Interface: I2C, SPI, UART, USB
• No. Of Pwm Channels: 5
• Core Size: 32 Bit
• Program Memory Size: 512 KB
• Core Processor: MIPS32® M4K™
• Speed: 80MHz
• Connectivity: Ethernet, I²C, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Program Memory Type: FLASH
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 2.3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 121-TFBGA
• Embedded Interface Type: I2C, SPI, UART, USB
• Rohs Compliant: Yes
• Processor Series: PIC32MX6xx
• Core: MIPS
• 3rd Party Development Tools: 52713-733, 52714-737
• Development Tools By Supplier: PG164130, DV164035, DV244005
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

PIC32MX575/675/695/775/795
12. Module: Timers
13. Module: SPI
14. Module: CAN
DS80480E-page 6
When the Timer module is first enabled and the
prescaler value is greater than 1, the number of
input clocks required to increment the timer from 0
to 1 is one input clock, not the value stated by the
prescaler.
Work around
None.
Affected Silicon Revisions
Outgoing data will be corrupted when in Frame
Slave mode with FRMCNT > 0 and the frame pulse
is coincident with the clock.
Work around
1. There is no work around for operation when
2. Provide a frame signal that precedes the clock
Affected Silicon Revisions
TXABAT, TXLARB and TXERR may erroneously
be cleared by an aborted read of the CiFIFOCONn
register. An aborted read occurs when a load
instruction in the CPU pipeline has started
execution, but is aborted due to an interrupt.
Work around
Disable interrupts before reading the contents of
the CiFIFOCONn register, and then re-enable
interrupts after reading the register.
Affected Silicon Revisions
A0
A0
A0
X
X
X
the Frame pulse is coincident with the clock.
signal.
15. Module: CAN
16. Module: CAN
17. Module: CAN
Requested aborts to a TX message via setting
CxCON.ABAT or clearing CiFIFOCON.TXREQ
may not complete. The CAN bus protocol is not
violated.
Work around
1.
2.
Affected Silicon Revisions
The
CFIFOCONx.UINC bits are not settable via a
normal Special Function Register (SFR) write.
Work around
Use the SET register operations to change the
state of these bits.
Affected Silicon Revisions
The DeviceNet™ message filtering does not
function.
Work around
Use hardware to filter the Standard Identifier (SID)
and use firmware to decode the DeviceNet
identifier.
Affected Silicon Revisions
A0
A0
A0
X
X
X
After a general abort request, firmware
should poll until CxCON.BUSY = 0 or wait
two message times. If CxCON.ABAT
remains high, the message was success-
fully aborted and the module must be reset
by clearing and setting bit CxCON.ON.
After a FIFO specific abort request,
firmware
CxCON.BUSY = 0 or wait two message
times. If CFIFOCONx.TXREQ remains
high,
aborted and the FIFO must be reset by
setting CFIFOCONx.FRESET and polling
until CFIFOCONx.FRESET = 0.
the
CFIFOCONx.FRESET
message
© 2010 Microchip Technology Inc.
should
was
poll
successfully
until
and