PIC32MX795F512L-80I/BG Microchip Technology, PIC32MX795F512L-80I/BG Datasheet - Page 78

• Manufacturer Part Number: PIC32MX795F512L-80I/BG
• Description: IC, 32BIT MCU, PIC32, 80MHZ, BGA-100
• Manufacturer: Microchip Technology
• Series: PIC® 32MXr

Specifications of PIC32MX795F512L-80I/BG

• Controller Family/series: PIC32
• Ram Memory Size: 128KB
• Cpu Speed: 80MHz
• No. Of Timers: 5
• Interface: CAN, I2C, SPI, UART, USB
• No. Of Pwm Channels: 5
• Core Size: 32 Bit
• Program Memory Size: 512 KB
• Core Processor: MIPS32® M4K™
• Speed: 80MHz
• Connectivity: CAN, Ethernet, I²C, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Program Memory Type: FLASH
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 2.3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 121-TFBGA
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Rohs Compliant: Yes
• Processor Series: PIC32MX7xx
• Core: MIPS
• 3rd Party Development Tools: 52713-733, 52714-737
• Development Tools By Supplier: PG164130, DV164035, DV244005
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

TABLE 4-13:
Legend:
Note
6630
6640
6800 U2MODE
6810
6820
6830
6840
6A00 U5MODE
6A10
6A20
6A30 U5RXREG
6A40
1:
U6RXREG
U2RXREG
U2TXREG
U5TXREG
U6BRG
U2BRG
U5BRG
U2STA
U5STA
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
This register has corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See
(1)
(1)
(1)
(1)
(1)
(1)
(1)
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
UART1 THROUGH UART6 REGISTER MAP (CONTINUED)
31/15
ON
ON
UTXISEL<1:0>
UTXISEL<1:0>
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
30/14
FRZ
FRZ
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
UTXINV
UTXINV
29/13
SIDL
SIDL
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
URXEN
URXEN
28/12
IREN
IREN
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
UTXBRK
UTXBRK
RTSMD
27/11
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
UTXEN
UTXEN
26/10
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
UTXBF
UTXBF
25/9
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
UEN<1:0>
ADM_EN
ADM_EN
TRMT
TRMT
24/8
RX8
TX8
RX8
TX8
RX8
—
—
—
—
—
—
—
—
—
—
—
BRG<15:0>
BRG<15:0>
BRG<15:0>
Bits
WAKE
WAKE
23/7
URXISEL<1:0>
URXISEL<1:0>
—
—
—
—
—
—
—
—
—
—
LPBACK
LPBACK
22/6
—
—
—
—
—
—
—
—
—
—
Section 12.1.1 “CLR, SET and INV Registers”
ABAUD
ADDEN
ABAUD
ADDEN
21/5
—
—
—
—
—
—
—
—
—
—
RXINV
RIDLE
RXINV
RIDLE
Transmit Register
Transmit Register
Receive Register
Receive Register
Receive Register
20/4
—
—
—
—
—
—
—
—
—
—
ADDR<7:0>
ADDR<7:0>
BRGH
BRGH
PERR
PERR
19/3
—
—
—
—
—
—
—
—
—
—
FERR
FERR
18/2
—
—
—
—
—
—
—
—
—
—
PDSEL<1:0>
PDSEL<1:0>
for more information.
OERR
OERR
17/1
—
—
—
—
—
—
—
—
—
—
URXDA
URXDA
STSEL
STSEL
16/0
—
—
—
—
—
—
—
—
—
—
0000
0000
0000
0000
0000
0000
0000
0110
0000
0000
0000
0000
0000
0000
0000
0000
0000
0110
0000
0000
0000
0000
0000
0000