PIC32MX795F512L-80I/BG Microchip Technology, PIC32MX795F512L-80I/BG Datasheet - Page 8

• Manufacturer Part Number: PIC32MX795F512L-80I/BG
• Description: IC, 32BIT MCU, PIC32, 80MHZ, BGA-100
• Manufacturer: Microchip Technology
• Series: PIC® 32MXr

Specifications of PIC32MX795F512L-80I/BG

• Controller Family/series: PIC32
• Ram Memory Size: 128KB
• Cpu Speed: 80MHz
• No. Of Timers: 5
• Interface: CAN, I2C, SPI, UART, USB
• No. Of Pwm Channels: 5
• Core Size: 32 Bit
• Program Memory Size: 512 KB
• Core Processor: MIPS32® M4K™
• Speed: 80MHz
• Connectivity: CAN, Ethernet, I²C, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Program Memory Type: FLASH
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 2.3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 121-TFBGA
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Rohs Compliant: Yes
• Processor Series: PIC32MX7xx
• Core: MIPS
• 3rd Party Development Tools: 52713-733, 52714-737
• Development Tools By Supplier: PG164130, DV164035, DV244005
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

PIC32MX575/675/695/775/795
25. Module: SPI
26. Module: PORTS
27. Module: SPI
DS80480E-page 8
In Slave mode, when entering Sleep mode after a
SPI transfer with SPI interrupts enabled, a false
interrupt may be generated that wakes the device.
This interrupt can be cleared; however, entering
Sleep may cause the condition to occur again.
Work around
Do not use SPI in Slave mode as a wake-up
source from Sleep.
Affected Silicon Revisions
When an I/O pin is set to output a logic high signal,
and is then changed to an input using the TRISx
registers, the I/O pin should immediately tri-state
and let the pin float. Instead, the pin will continue
to partially drive a logic high signal out for a period
of time.
Work around
The pin should be driven low, prior to being tri-
stated, if it is desirable for the pin to tri-state
quickly.
Affected Silicon Revisions
Byte writes to the SPISTAT register are not
decoded correctly. A byte write to byte zero of
SPISTAT is actually performed on both byte zero
and byte one. A byte write to byte one of SPISTAT
is ignored.
Work around
Only perform word operations on the SPISTAT
register.
Affected Silicon Revisions
A0
A0
A0
X
X
X
28. Module: SPI
29. Module: CAN
30. Module: UART
In Frame mode the module is not immediately
ready for further transfers after clearing the
SPITUR bit. The SPITUR bit will be cleared by
hardware before the SPI state machine is
prepared for the next operation.
Work around
Firmware must wait at least four bit times before
writing to the SPI registers after clearing the
SPITUR bit.
Affected Silicon Revisions
When an abort request occurs concurrently with a
successful message transmission, and additional
messages remain in the FIFO, these remaining
messages are not transmitted and the TXABAT bit
does not reflect the abort.
Work around
The actual FIFO status can be determined by the
FIFO pointers CFIFOCI and CFIFOUA.
Affected Silicon Revisions
The UART module is not fully IrDA
The module does not detect the 1.6 µs minimum
bit width at all baud rates as defined in the IrDA
specification. The module does detect the 3/16 bit
width at all baud rates.
Work around
None.
Affected Silicon Revisions
A0
A0
A0
X
X
X
© 2010 Microchip Technology Inc.
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compliant.