SAK-C164CI-8E25M Infineon Technologies, SAK-C164CI-8E25M Datasheet - Page 39

• Manufacturer Part Number: SAK-C164CI-8E25M
• Description: IC, 16BIT MCU, 64K OTP, MQFP80, 164
• Manufacturer: Infineon Technologies

Specifications of SAK-C164CI-8E25M

• Core Size: 16bit
• No. Of I/o's: 59
• Program Memory Size: 64KB
• Ram Memory Size: 4KB
• Cpu Speed: 25MHz
• Oscillator Type: External Only
• No. Of Timers: 5
• Digital Ic Case Style: MQFP
• Supply Voltage: RoHS Compliant
• Controller Family/series: C164CI
• Peripherals: ADC
• Rohs Compliant: Yes

Phase Locked Loop
For all other combinations of pins P0.15-13 (P0H.7-5) during reset the on-chip phase locked loop is
enabled and provides the CPU clock (see table above). The PLL multiplies the input frequency by
the factor F which is selected via the combination of pins P0.15-13 (ie. f
F’th transition of f
synchronization is done smoothely, ie. the CPU clock frequency does not change abruptly.
Due to this adaptation to the input clock the frequency of f
to f
The timings listed in the AC Characteristics that refer to TCLs therefore must be calculated using the
minimum TCL that is possible under the respective circumstances.
The actual minimum value for TCL depends on the jitter of the PLL. As the PLL is constantly
adjusting its output frequency so it corresponds to the applied input frequency (crystal or oscillator)
the relative deviation for periods of more than one TCL is lower than for one single TCL (see formula
and figure below).
For a period of N * TCL the minimum value is computed using the corresponding deviation D
So for a period of 3 TCLs (ie. N = 3): D
and (3TCL)
This is especially important for bus cycles using waitstates and eg. for the operation of timers, serial
interfaces, etc. For all slower operations and longer periods (eg. pulse train generation or
measurement, lower baudrates, etc.) the deviation caused by the PLL jitter is neglectible.
Figure 10
Approximated Maximum PLL Jitter
Semiconductor Group
XTAL
4
3
2
1
Max.jitter [%]
. The slight variation causes a jitter of f
2
min
= 3TCL
4
TCL
XTAL
min
NOM
the PLL circuit synchronizes the CPU clock to the input clock. This
= TCL
8
* (1 - 3.8 / 100) = 3TCL
NOM
* (1 - D
3
= 4 - 3 /15 = 3.8%,
N
16
CPU
/ 100)
39
which also effects the duration of individual TCLs.
NOM
* 0.962 (57.72 nsec @ f
This approximated formula is valid for
1
CPU
D
where N = number of consecutive TCLs
and 1
N
N
= (4 - N /15) [%],
is constantly adjusted so it is locked
40 and 10MHz
N
40.
CPU
= f
XTAL
CPU
f
CPU
* F). With every
= 25 MHz).
32
25MHz.
C164CI
1998-02
N
N
: