DSPIC30F1010-20E/SO Microchip Technology, DSPIC30F1010-20E/SO Datasheet - Page 13

• Manufacturer Part Number: DSPIC30F1010-20E/SO
• Description: 6KB, Flash, 256bytes-RAM, 30MIPS, 21I/O, 16-bit Family,nanoWatt 28 SOIC .300in T
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F1010-20E/SO

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 20 MIPS
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 21
• Program Memory Size: 6KB (2K x 24)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 28-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DM300023 - KIT DEMO DSPICDEM SMPS BUCKDV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLE
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

26. Module: I
27. Module: I
28. Module: I
© 2008 Microchip Technology Inc.
Writing to I2CxTRN during a Start bit transmission
generates a write collision, indicated by the
IWCOL (I2CxSTAT<7>) bit being set. In this state,
additional writes to the I2CxTRN register should
be blocked. However, in this condition, the
I2CxTRN register can be written, although
transmissions will not occur until the IWCOL bit is
cleared in software.
Work around
After each write to the I2CxTRN register, read the
IWCOL bit to ensure a collision has not occurred.
If the IWCOL bit is set, it must be cleared in
software and I2CxTRN must be rewritten.
The ACKSTAT bit (I2CxSTAT<15>) only reflects
the received ACK/NACK status for Master
transmissions, but not for Slave transmissions. As
a result, a Slave cannot use this bit to determine if
it received an ACK or a NACK from a Master. In
future silicon revisions, the ACKSTAT bit will
reflect received ACK/NACK status for both Master
and Slave transmissions.
Work around
After transmitting a byte, the Slave should poll the
SDA line (subject to a time out period dependent
on the application) to determine if an ACK (‘0’) or
a NACK (‘1’) was received.
The D_A Status bit (I2CxSTAT<5>) gets set on a
slave data reception in the I2CxRCV register, but
does not get set on a slave write to the I2CxTRN
register. In future silicon revisions, the D_A bit will
get set on a slave write to I2CxTRN.
Work around
Use the D_A Status bit only for determining slave
reception status and not slave transmission status.
2
2
2
C Module
C Module
C Module
29. Module: UART Module
TABLE 3:
30. Module: UART Module
Idle State = ‘1’
Idle State = ‘0’
Type of Signal
Transmission
dsPIC30F1010/202X
Used for
The UART module can be used to transmit and
receive IrDA
transceiver by setting the IREN bit in the UxMODE
register. In this mode, the operation of the RXINV
bit enables reception of signals with an Idle state
of either ‘1’ or ‘0’. The operation of this bit is the
inverse
“dsPIC30F1010/202X
(DS70178).
The signal received from an IrDA transceiver can
have an idle state of ‘1’ or ‘0’. Table 3 summarizes
how UART receptions will occur when used with
the IrDA decoder.
Work around
Invert the state of RXINV bit in the UxMODE
register.
If the idle state of the received signal is ‘1’,
configure RXINV = 1. If the idle state of the received
signal is ‘0’, configure RXINV = 0.
The auto-baud feature may miscalculate for
certain baud rate and clock speed combinations,
resulting in a BRG value that is greater than or
lesser than the expected value by 1. This may
result in reception or transmission failures.
Work around
Test the auto-baud rate at various clock speed and
baud rate combinations that would be used in an
application. If an inaccurate BRG value is
generated, manually correct the baud rate in user
software.
of
®
the
RXINV = 0
RXINV = 1
RXINV = 0
RXINV = 1
signals with the use of an IrDA
RXINV bit
State of
stated
Device
operation
May be erroneous
Error-free
Error-free
May be erroneous
UART reception
DS80290J-page 13
Data
in
Sheet”
the