EP7309-CR Cirrus Logic Inc, EP7309-CR Datasheet - Page 40

• Manufacturer Part Number: EP7309-CR
• Description: 32-Bit Microcontroller IC
• Manufacturer: Cirrus Logic Inc

Specifications of EP7309-CR

• Controller Family/series: (ARM7)
• Core Size: 32 Bit
• No. Of Timers 8/12/16/32 Bits: 0 / 0 / 2 / 0
• Interface: SSI, UART
• Embedded Interface Type: SSI, UART
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

EP7309
High-Performance, Low-Power System on Chip
40
Ball Location
B10
B11
B12
B13
B14
B15
B16
C10
C11
C12
C13
C14
C15
C16
D10
D11
D12
D13
D14
D15
D16
B7
B8
B9
C1
C2
C3
C4
C5
C6
C7
C8
C9
D1
D2
D3
D4
D5
D6
D7
D8
D9
E1
E2
E3
E4
E5
E6
Table 21. 256-Ball PBGA Ball Listing (Continued)
VDDCORE
nEXTPWR
nURESET
WAKEUP
EXPRDY
VSSRTC
nPWRFL
MOSCIN
EXPCLK
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
WRITE
VDDIO
VDDIO
RXD[2]
VSSIO
VSSIO
VSSIO
VSSIO
VSSIO
VSSIO
VSSIO
VSSIO
VSSIO
VSSIO
nCS[2]
nMWE
VSSIO
WORD
VSSIO
nCS[0]
Name
DD[2]
nPOR
CL[1]
CL[2]
PB[7]
D[1]
A[2]
A[4]
A[5]
D[4]
D[7]
D[8]
N/C
TDI
Core ground Real time clock ground
Core power Digital core power, 2.5V
Pad ground I/O ground
Pad ground I/O ground
Pad ground I/O ground
Pad ground I/O ground
Pad ground I/O ground
Pad ground I/O ground
Pad ground I/O ground
Pad ground I/O ground
Pad ground I/O ground
Pad ground I/O ground
Pad ground I/O ground
Pad ground I/O ground
Pad power
Pad power
Pad power
Pad power
Pad power
Pad power
Pad power
Type
I/O
I/O
I/O
I/O
O
O
O
O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
LCD serial display data
LCD line clock
Data I/O
System byte address
System byte address
System byte address
System wake up input
Digital I/O power, 3.3V
User reset input
Digital I/O power, 3.3V
Expansion clock input
Digital I/O power, 3.3V
Digital I/O power, 3.3V
Digital I/O power, 3.3V
Power-on reset input
External power supply sense input
Transfer direction
Expansion port ready input
Digital I/O power, 3.3V
Chip select out
ROM, expansion write enable
LCD pixel clock out
Data I/O
Power fail sense input
Main oscillator input
Digital I/O power, 3.3V
Data I/O
Data I/O
UART 2 receive data input
GPIO port B
JTAG data input
Word access select output
Chip select out
Description
©
Copyright Cirrus Logic, Inc. 2005
(All Rights Reserved)
Ball Location
G10
G11
G12
G13
G14
G15
G16
E10
E11
E12
E13
E14
E15
E16
F10
F11
F12
F13
F14
F15
F16
G1
G2
G3
G4
G5
G6
G7
G8
G9
E7
E8
E9
F1
F2
F3
F4
F5
F6
F7
F8
F9
H1
H2
H3
H4
H5
Table 21. 256-Ball PBGA Ball Listing (Continued)
nMEDCHG/nBROM
PB[1]/PRDY[2]
RUN/CLKEN
nBATCHG
VSSOSC
VSSRTC
VSSRTC
VSSRTC
VSSRTC
VDDIO
TXD[2]
BATOK
VDDIO
VDDIO
VSSIO
VSSIO
VSSIO
VSSIO
VSSIO
VSSIO
Name
DD[3]
DD[0]
D[10]
PB[5]
PB[3]
D[11]
PB[4]
PB[6]
D[12]
D[13]
PA[7]
PA[5]
PA[4]
PA[6]
FRM
TDO
N/C
A[0]
D[5]
D[9]
N/C
A[1]
D[6]
D[3]
A[7]
A[8]
A[9]
Core ground Real time clock ground
RTC ground Real time clock ground
RTC ground Real time clock ground
RTC ground Real time clock ground
Pad ground I/O ground
Pad ground I/O ground
Pad ground I/O ground
Pad ground I/O ground
Pad ground I/O ground
Pad ground I/O ground
Pad power
Pad power
Pad power
Oscillator
ground
Type
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
O
O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
I
LCD frame synchronization pulse
System byte address
Data I/O
PLL ground
Media change interrupt input / internal
rom boot enable
Digital I/O power, 3.3V
Data I/O
Data I/O
GPIO port B
GPIO port B
UART 2 transmit data output
Run output / clock enable output
LCD serial display data
System byte address
Data I/O
Battery ok input
Battery changed sense input
Data I/O
Digital I/O power, 3.3V
GPIO port B / CL-PS6700 interface
signal
Digital I/O power, 3.3V
JTAG data out
GPIO port B
GPIO port B
LCD serial display data
Data I/O
System byte address
System byte address
System byte address
Data I/O
Data I/O
GPIO port A
GPIO port A
GPIO port A
GPIO port A
Description
DS507F1