PIC16F767-E/SP Microchip Technology, PIC16F767-E/SP Datasheet - Page 2

• Manufacturer Part Number: PIC16F767-E/SP
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,DIP,28PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F767-E/SP

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 25
• Program Memory Size: 14KB (8K x 14)
• Program Memory Type: FLASH
• Ram Size: 368 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 28-DIP (0.300", 7.62mm)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC16F7X7
2. Module: Internal RC Oscillator IOFS bit
EXAMPLE 1:
DS80177E-page 2
The device data sheet states when an INTOSC
frequency is selected (125, 250, 500 kHz, 1, 2, 4,
8 MHz), the frequency will be stable when the
IOFS bit becomes set (IOFS = 1) at 4 ms. The
following applies for applications relying on time
dependent code.
Under the following conditions, any of the INTOSC
frequencies may not be stable when IOFS
becomes set (IOFS = 1). Devices may vary from
one to the next and may take as long as 60 ms to
become stable.
1. Wake from Sleep, internal RC oscillator is
2. POR is executed, internal RC oscillator is
DlyVarH
DlyVarL
;Load the delay variable DlyVarH with the following value for the selected frequency:
delay
dly_loop
RETURN
selected via the SCS bits or Configuration
Word 1 and the IRCF bits are configured for an
INTOSC frequency.
selected via the SCS bits or Configuration
Word 1 and the IRCF bits are configured for an
INTOSC frequency.
;125kHz 0x0300
;250kHz 0x0600
;500kHz 0x0C00
;1MHz
;2MHz
;4MHz
CLRF
MOVLW
MOVWF
DECFSZ
GOTO
DECFSZ
GOTO
equ
equ
0x1900
0x3100
0x6200
DlyVarL
0x62
DlyVarH
DlyVarL,f
dly_loop
DlyVarH,f
dly_loop
DELAY ROUTINE
<define address based on application requirements>
<define address based on application requirements>
;insure the correct data memory bank is selected
; for access of data variables
;initialize low delay variable
;initialize high delay variable
;decrement low variable
;decrement high variable
;delay done
3. The INTRC (31.25 kHz) is clocking the device
4. An alternative oscillator selection is clocking
Work around
Implement the following software delay shown in
Example 1 after an INTOSC frequency has been
enabled and before any frequency dependent appli-
cation code is executed. This routine will delay
application execution approximately 2K-150K T
(instruction cycles are dependent upon the INTOSC
frequency) to ensure a stable INTOSC frequency.
Date Codes that pertain to this issue:
All date codes.
and a switch to an INTOSC frequency is
executed via modification of the IRCF bits.
the device (i.e., HS mode) and a clock switch
to the internal RC oscillator is executed via the
SCS bits with the IRCF bits configured for an
INTOSC frequency.
 2004 Microchip Technology Inc.
CY