PIC18F6722T-E/PT Microchip Technology, PIC18F6722T-E/PT Datasheet - Page 6
![IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,TQFP,64PIN,PLASTIC](/photos/6/81/68123/c04-066_pf_sml.jpg)
PIC18F6722T-E/PT
Manufacturer Part Number
PIC18F6722T-E/PT
Description
IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,TQFP,64PIN,PLASTIC
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.DV164136.pdf
(6 pages)
3.DV164136.pdf
(446 pages)
4.PIC18F8627T-IPT.pdf
(44 pages)
5.PIC18LF6627-IPT.pdf
(16 pages)
Specifications of PIC18F6722T-E/PT
Rohs Compliant
YES
Core Processor
PIC
Core Size
8-Bit
Speed
25MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
54
Program Memory Size
128KB (64K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
3.8K x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
64-TFQFP
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3936 B
Interface Type
SPI, I2C, EUSART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
54
Number Of Timers
5
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM183032, DM183022
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 12 Channel
A/d Bit Size
10 bit
A/d Channels Available
12
Height
1 mm
Length
10 mm
Supply Voltage (max)
5.5 V
Supply Voltage (min)
4.2 V
Width
10 mm
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
MA180020 - MODULE PLUG-IN HPC EXPL 18F87J11
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F6722T-E/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
PIC18F6627/6722/8627/8722
16. Module: External Memory Bus
17. Module: MSSP
18. Module: MSSP
DS80221C-page 6
For PIC18F8XXX devices, the Stack Pointer may
incorrectly increment during a table read operation if
external memory bus wait states are enabled (i.e.,
Configuration bit, WAIT, is clear (CONFIG3L<7> = 0)
and WAIT<1:0> bits (MEMCON<5:4>) are not equal
to ‘11’).
Work around
If using the external memory bus and performing
TBLRD
state (CONFIG3L<7>
(MEMCON<5:4> are not equal to ‘11’), disable
interrupts by clearing the GIE/GIEH (INTCON<7>)
and PEIE/GIEL (INTCON<6>) bits prior to
executing any TBLRD operation.
In an I
unaddressed slave may respond to bus activity
when data on the bus matches its address. The
first occurrence will set the BF bit. The second
occurrence will set the BF and SSPOV bits. In both
situations, the SSPxIF bit is not set and an inter-
rupt will not occur. The device will vector to the
Interrupt Service Routine only if the interrupt is
enabled and an address match occurs.
Work around
The I
I
Setting the SEN bit initiates a Start sequence on
the bus, after which, the SEN bit is cleared auto-
matically by hardware. If the SEN bit is set again
(without an address byte being transmitted), a
Start sequence will not commence and the SEN bit
will not be cleared. This condition causes the bus
to remain in an active state. The system is idle
when ACKEN, RCEN, PEN, RSEN, and SEN are
clear.
Work around
Set the PEN or RSEN bit to transmit a Stop or
Repeated Start sequence, although the SEN bit
may still be set, indicating the bus is active. After
the sequence has completed, the PEN, RSEN and
SEN bits will be clear, indicating the bus is idle.
Clearing and setting the SSPEN bit will also reset
the I
SEN status bits.
2
C address match to maintain normal operation.
2
2
C peripheral and clear the PEN, RSEN and
C slave must clear the SSPOV bit after each
2
C™ system with multiple slave nodes, an
operations
with
=
0
a
and
non-zero
WAIT<1:0>
wait
19. Module: MSSP
20. Module: MSSP
In SPI mode, the Buffer Full flag (BF bit in the
SSPxSTAT register), the Write Collision Detect bit
(WCOL in SSPxCON1) and the Receive Overflow
Indicator bit (SSPOV in SSPxCON1) are not reset
upon disabling the SPI module (by clearing the
SSPEN bit in the SSPxCON1 register).
For example, if SSPxBUF is full (BF bit is set) and
the MSSP module is disabled and re-enabled, the
BF bit will remain set. In SPI Slave mode, a sub-
sequent write to SSPxBUF will result in a write
collision. Also, if a new byte is received, a receive
overflow will occur.
Work around
Ensure that if the buffer is full, SSPxBUF is read
(thus clearing the BF flag) and WCOL is clear
before disabling the MSSP module. If the module
is configured in SPI Slave mode, ensure that the
SSPOV bit is clear before disabling the module.
In I
work correctly.
Work around
Use a BRG value greater than ‘0’ by setting
SSPxADD ≥ ‘1’.
2
C Master mode, the BRG value of ‘0’ may not
© 2006 Microchip Technology Inc.