APDS-9300-020 Avago Technologies US Inc., APDS-9300-020 Datasheet

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... Application Support Information The Application Engineering Group is available to assist you with the application design associated with APDS- 9300 ambient light photo sensor module. You can contact them through your local sales representatives for addi- tional details. Features • ...

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... Ordering Information Part Number Packaging Type APDS-9300-020 Tape and Reel Functional Block Diagram Ch0 (Visible + IR 2 3.0 V Ch1 (IR) GND I/O Pins Configuration Table Pin Symbol Description 1 V Voltage Supply DD 2 GND Ground 3 ADDR SEL Address Select 4 SCL Serial Clock 5 SDA Serial Data 6 INT Interrupt 2 Package 6-pins Chipled package Address Select ...

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Absolute Maximum Ratings Parameter Supply voltage Digital output voltage range Digital output current Storage temperature range ESD tolerance Recommended Operating Conditions Parameter Supply Voltage Operating Temperature SCL, SDA input low voltage SCL, SDA input high voltage Electrical Characteristics Parameter Supply current INT, SDA output low voltage Leakage current 3 Symbol Min -0 -40 stg human body model - ...

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Operating Characteristics, High Gain (16X), V Parameter Symbol Oscillator frequency fosc Dark ADC count value Full scale ADC count value (Note 6) ADC count value ADC count value ratio: Ch1/ Ch0 Irradiance responsivity Re Illuminance responsivity Rv ADC count value ratio: Ch1/ Ch0 Illuminance responsivity, Rv low gain mode (Note 7) (Sensor Lux) /(actual Lux), high gain mode (Note 2 ºC, (unless otherwise noted) (see Notes ...

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Notes: 2. Optical measurements are made using small–angle incident radiation from light–emitting diode optical sources. Visible 640 nm LEDs and infrared 940 nm LEDs are used for final product testing for compatibility with high–volume production. 3. The 640 nm irradiance Ee is supplied by an AlInGaP light–emitting diode with the following characteristics: peak wavelength lp = 640 nm and spectral halfwidth Dl½ nm. 4. The 940 nm irradiance Ee is supplied by a GaAs light–emitting diode with the following characteristics: peak wavelength lp = 940 nm and spectral halfwidth Dl½ nm. 5. Integration time Tint, is dependent on internal oscillator frequency (fosc) and on the integration field value in the timing register as described in the Register Set section. For nominal fosc = 735 kHz, nominal Tint = (number of clock cycles)/fosc. Field value 00: Tint = (11 • 918)/fosc = 13.7 ms Field value 01: Tint = (81 • 918)/fosc = 101 ms Field value 10: Tint = (322 • 918)/fosc = 402 ms Scaling between integration times vary proportionally as follows: 11/322 = 0.034 (field value 00), 81/322 = 0.252 (field value 01), and 322/322 = 1 (field value 10). 6. Full scale ADC count value is limited by the fact that there is a maximum of one count per two oscillator frequency periods and also by a 2–count offset. Full scale ADC count value = ((number of clock cycles)/ Field value 00: Full scale ADC count value = ((11 • 918)/ 5047 ...

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... C Receive Byte Format (HIGH) (SUSTA (HDDAT) (SUDAT) Start t (LOWSEXT) SCL SCL ACK ACK t t (LOWMEXT) (LOWMEXT R ACK by APDS-9300 R ACK by APDS-9300 t (SUSTO) S Stop t (LOWMEXT ACK by APDS-9300 Frame 2 Command Byte NACK by Master Frame 2 Data Byte From APDS-9300 P 9 Stop by Master Stop by Master ...

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... Interface and control of the APDS-9300 is accomplished through a two–wire serial interface to a set of registers that provide access to device control functions and out- put data. The serial interface is compatible to I Mode. The APDS-9300 offers three slave addresses that are selectable via an external pin (ADDR SEL). The slave address options are shown in Table 1. Table 1. Slave Address Selection ...

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... I C Protocols Each Send and Write protocol is, essentially, a series of bytes. A byte sent to the APDS-9300 with the most sig- nificant bit (MSB) equal to 1 will be interpreted as a COM- MAND byte. The lower four bits of the COMMAND byte form the register select address (see Table 2), which is used to select the destination for the subsequent byte(s) received ...

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... Register Set The APDS-9300 is controlled and monitored by sixteen registers (three are reserved) and a command register accessed through the serial interface. These registers provide for a variety of control functions and can be read to determine re- sults of the ADC conversions. The register set is summarized in Table 2. Table 2. Register Address Address Register Name -- COMMAND 0h CONTROL 1h TIMING 2h THRESHLOWLOW 3h THRESHLOWHIGH 4h THRESHHIGHLOW 5h THRESHHIGHHIGH 6h INTERRUPT CRC DATA0LOW Dh DATA0HIGH Eh DATA1LOW Fh DATA1HIGH The mechanics of accessing a specific register depends on the specific I protocols ...

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... Interrupt clear. Clears any pending interrupt. This bit is a write–one–to–clear bit self clearing. WORD indicates that this I Resv 4 Reserved. Write as 0. ADDRESS 3:0 Register Address. This field selects the specific control or status register for following write and read com- mands according to Table 2. Control Register (0h) The CONTROL register contains two bits and is primarily used to power the APDS-9300 device up and down as shown in Table 4. Table 4. Control Register 7 6 Resv Resv 0h Reset Value Field BIT Description Resv 7:2 Reserved ...

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... Table 6. Integration Time Integ Field Value Scale 00 0.034 01 0.252 The manual timing control feature is used to manually start and stop the integration time period particular integra- tion time period is required that is not listed in Table 6, then this feature can be used. For example, the manual timing control can be used to synchronize the APDS-9300 device with an external light source (e.g. LED). A start command to begin integration can be initiated by writing this bit field. Correspondingly, the integration can be stopped by simply writing the same bit field Resv GAIN MANUAL Nominal Integration Time 13 ...

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... Word protocol should be used to write byte–paired registers. For example, the THRESHLOWLOW and THRESHLOWHIGH registers (as well as the THRESHHIGHLOW and THRESHHIGHHIGH registers) can be written together to set the 16–bit ADC value in a single transaction. Interrupt Control Register (6h) The INTERRUPT register controls the extensive interrupt capabilities of the APDS-9300. The APDS-9300 permits tradi- tional level–style interrupts. The interrupt persist bit field (PERSIST) provides control over when interrupts occur. A value of 0 causes an interrupt to occur after every integration cycle regardless of the threshold settings. A value of 1 results in an interrupt after one integration time period outside the threshold window. A value of N (where through15) results in an interrupt only if the value remains outside the threshold window for N consecutive integration cycles ...

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Table 9. Interrupt Control Select Intr Field Value 00 01 Table 10. Interrupt Persistence Select Persist Field Value 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 ID Register (Ah) The ID register provides the value for both the part number and silicon revision number for that part number read–only register, whose value never changes. Table ...

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ADC Channel Data Registers (Ch - Fh) The ADC channel data are expressed as 16–bit values spread across two registers. The ADC channel 0 data registers, DATA0LOW and DATA0HIGH provide the lower and upper bytes, respectively, of the ADC value of channel 0. Registers DATA1LOW and DATA1HIGH provide the lower and upper bytes, respectively, of the ADC value of channel 1. All channel data registers are read–only and default to 00h on power up. Table 12. ADC Channel Data Registers Register Address Bits DATA0LOW Ch 7:0 DATA0HIGH Dh 7:0 DATA1LOW Eh 7:0 DATA1HIGH Fh 7:0 The upper byte data registers can only be read following a read to the corresponding lower byte register. When the lower byte register is read, the upper eight bits are strobed into a shadow register, which is read by a subsequent read to the upper byte. The upper register will read the correct value even if additional ADC integration cycles end between the reading of the lower and upper registers. NOTE: The Read Word protocol can be used to read byte–paired registers. For example, the DATA0LOW and DATA0HIGH registers (as well as the DATA1LOW and DATA1HIGH registers) may be read together to obtain the 16–bit ADC value in a single transaction 14 ...

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... APDS-9300 PACKAGE OUTLINE Notes: 1. All dimensions are in millimeters. Dimension tolerance is ±0.2 mm unless otherwise stated PCB Pad Layout The suggested PCB layout is given below: Notes: 1. All linear dimensions are in millimeters 15 Pin Pin 2 : GND Pin 3 : ADDR SEL Pin 4 : SCL Pin 5 : SDA Pin 6 : INT UNIT: mm Tolerance: +/- 0.2mm ...

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... Tape and Reel Dimensions - APDS-9300 16 ...

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... Moisture Proof Packaging Chart All APDS-9300 options are shipped in moisture proof package. Once opened, moisture absorption begins. This part is compliant to JEDEC Level 3. YES NO BAKING IS NECESSARY BAKING CONDITIONS CHART Recommended Storage Conditions Storage Temperature 10°C to 30°C Relative Humidity Below 60% RH Time from Unsealing to Soldering After removal from the bag, the parts should be soldered within seven days if stored at the recommended storage conditions. When MBB (Moisture Barrier Bag) is opened ...

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Recommended Reflow Profile 255 230 217 200 180 150 R1 120 HEAT UP Process Zone Heat Up Solder Paste Dry Solder Reflow Cool Down Time maintained above liquidus point , 217°C Peak Temperature Time within 5°C of actual Peak Temperature Time 25°C to Peak Temperature The reflow profile is a straight-line representation of a nominal temperature profile ...

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... Figure A1. Recommended Window Design 19 Table A1 and Figure A2 show the recommended dimen- sions of the window. These dimension values are based on a window thickness of 1.0mm with a refractive index 1.585. The window should be placed directly on top of the light sensitive area of APDS-9300 (see Figure A3) to achieve better performance flat window with a light pipe is used, dimension D2 should be 1.55mm to optimize the performance of APDS-9300 ...

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... Figure A3. APDS-9300 Light Sensitive Area Notes: 1. All dimensions are in millimeters 2. All package dimension tolerance in ± 0.2mm unless otherwise specified A2: Optical Window Material The material of the window is recommended to be poly- carbonate. The surface finish of the plastic should be smooth, without any texture. The recommended plastic material for use as a window is available from Bayer AG and Bayer Antwerp N. V. (Europe), Bayer Corp ...

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... Pin 3 ** ADDR_SEL Pin 2: GND ** Note: ADDR_SEL Float : Slave address is 0111001 Figure B1. Application circuit for APDS-9300 The power supply lines must be decoupled with a 0.1 uF capacitor placed as close to the device package as pos- sible, as shown in Figure B1. The bypass capacitor should have low effective series resistance (ESR) and low effec- tive series inductance (ESI), such as the common ceramic ...