ISL29012IROZ-T7 Intersil, ISL29012IROZ-T7 Datasheet - Page 5

• Manufacturer Part Number: ISL29012IROZ-T7
• Description: IC SENSOR LIGHT-DGTL I2C 6-ODFN
• Manufacturer: Intersil

Specifications of ISL29012IROZ-T7

• Wavelength: 540nm
• Output Type: I²C™
• Package / Case: 6-ODFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Register Set
There are eight registers that are available in the ISL29012. Table 1 summarizes the available registers and their functions.
Command Register 00(hex)
The Read/Write command register has five functions:
b1xxx_xxxx
bx1xx_xxxx
ADDRESS
2. ADCPD; Bit 6. This function puts the device in a
3. Timing Mode; Bit 5. This function determines whether the
1. Enable; Bit 7. This function either resets the ADC or enables
ADDR
00h
01h
02h
03h
04h
05h
06h
07h
BIT 7
BIT 6
the ADC in normal operation. A logic 0 disables ADC to
reset-mode. A logic 1 enables ADC to normal operation.
power-down mode. A logic 0 puts the device in normal
operation. A logic 1 powers down the device.
integration time is done internally or externally. In Internal
Timing Mode, integration time is determined by an
internal dual speed oscillator (f
8, 12,16) counter inside the ADC. In External Timing
Mode, integration time is determined by the time between
three consecutive external-sync sync_
commands.
0
1
0
1
LSB SENSOR
Threshold_LO
Threshold_HI
MSB TIMER
REG NAME
COMMAND
LSB TIMER
CONTROL
SENSOR
Disable ADC-core to reset-mode (default)
Enable ADC-core to normal operation
Normal operation (default)
Power Down
REGISTER
Interrupt
Interrupt
sync_I
TABLE 2. WRITE ONLY REGISTERS
MSB
clar_int
NAME
2
C Writing a logic 1 to this address bit ends the
TABLE 3. ENABLE
TABLE 4. ADCPD
current ADC-integration and starts another.
Used only with External Timing Mode.
Writing a logic 1 to this address bit clears
the interrupt.
ITH_LO7
ITH_HI7
ADCE
S15
T15
S7
T7
7
0
5
OPERATION
OPERATION
OSC
DESCRIPTION
ITH_LO6
FUNCTIONS/
ITH_HI6
ADCPD
S14
T14
S6
T6
), and the n-bit (n = 4,
6
0
I
2
C
pulses
INT_FLAG
ITH_LO5
ITH_HI5
TIMM
S13
T13
S5
T5
5
TABLE 1. REGISTER SET
ISL29012
ITH_LO4
ITH_HI4
S12
T12
S4
T4
4
0
0
* n = 4, 8, 12,16 depending on the number of clock cycles
function.
.
4. Photodiode Select Mode; Bits 3 and 2. Setting Bit 3 and
5. Width; Bits 1 and 0. This function determines the number
BITS 3:2
BITS 1:0
BIT 5
ITH_LO3
ITH_HI3
ADCM1
Bit 2 to 1 and 0 enables ADC to give light count DATA
output.
of clock cycles per conversion. Changing the number of
clock cycles does more than just change the resolution of
the device. It also changes the integration time, which is
the period the device’s analog-to-digital (A/D) converter
samples the photodiode current signal for a lux
measurement.
GAIN1
0:0
0:1
1:0
1:1
0:0
0:1
1:0
1:1
TABLE 6. PHOTODIODE SELECT MODE; BITS 2 AND 3
0
1
BIT
S11
T11
S3
T3
3
Internal Timing Mode. Integration time is internally timed
determined by f
External Timing Mode. Integration time is externally
timed by the I
Disable ADC
Disable ADC
Light count DATA output in signed (n-1) bit *
No operation.
2
2
2
2
16
12
8
4
= 256
= 16
ITH_LO2
ITH_HI2
ADCM0
= 65,536
= 4,096
GAIN0
S10
T10
S2
T2
2
TABLE 5. TIMING MODE
NUMBER OF CLOCK CYCLES
TABLE 7. WIDTH
2
C host.
OSC
ITH_LO1
ITH_HI1
RES1
IC1
, R
S1
S9
T1
T9
1
OPERATION
EXT
MODE
, and number of clock cycles.
ITH_LO0
ITH_HI0
RES0
IC0
S0
S8
T0
T8
0
December 10, 2008
DEFAULT
00h
00h
FFh
00h
00h
00h
00h
00h
FN6476.1