ACPL-P302-060E Avago Technologies US Inc., ACPL-P302-060E Datasheet - Page 12

• Manufacturer Part Number: ACPL-P302-060E
• Description: Gate Drive Optocoupler, LF+VDE
• Manufacturer: Avago Technologies US Inc.

Specifications of ACPL-P302-060E

• Voltage - Isolation: 3750Vrms
• Number Of Channels: 1, Unidirectional
• Current - Output / Channel: 400mA
• Propagation Delay High - Low @ If: 300ns @ 7mA
• Current - Dc Forward (if): 12mA
• Input Type: DC
• Output Type: Push-Pull, Totem-Pole
• Mounting Type: Surface Mount
• Package / Case: SO-6
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

LED Drive Circuit Considerations for Ultra High CMR Per-
formance
Without a detector shield, the dominant cause of opto-
coupler CMR failure is capacitive coupling from the input
side of the optocoupler, through the package, to the
detector IC as shown in Figure 19. The ACPL-P302/W302
improves CMR performance by using a detector IC with
an optically transparent Faraday shield, which diverts the
capacitively coupled current away from the sensitive IC
circuitry. However, this shield does not eliminate the ca-
pacitive coupling between the LED and optocoupler pins
5-8 as shown in Figure 20. This capacitive coupling causes
perturbations in the LED current during common mode
transients and becomes the major source of CMR failures
for a shielded optocoupler. The main design objective of
a high CMR LED drive circuit becomes keeping the LED in
the proper state (on or off ) during common mode tran-
sients. For example, the recommended application circuit
(Figure 17), can achieve 10 kV/μs CMR while minimizing
component complexity.
Techniques to keep the LED in the proper state are dis-
cussed in the next two sections.
Figure 19. Optocoupler Input to Output Capacitance Model for Unshielded
Optocouplers.
Figure 20. Optocoupler Input to Output Capacitance Model for Shielded
Optocouplers.
CMR with the LED On (CMR
A high CMR LED drive circuit must keep the LED on during
common mode transients. This is achieved by overdriv-
ing the LED current beyond the input threshold so that
it is not pulled below the threshold during a transient. A
minimum LED current of 7 mA provides adequate margin
over the maximum I
12
1
1
2
2
3
3
1
1
2
2
3
3
C
C
C
C
C
C
C
C
LEDP
LEDP
LEDN
LEDN
LEDP
LEDP
LEDN
LEDN
C
C
LED01
LED01
SHIELD
SHIELD
C
C
LED02
LED02
FLH
of 5 mA to achieve 10 kV/μs CMR.
H
)
6
6
5
5
4
4
6
6
5
5
4
4
CMR with the LED Off (CMR
A high CMR LED drive circuit must keep the LED off (V
d V
during a -dV
flowing through C
V
veloped across the logic gate is less than V
will remain off and no common mode failure will occur.
Figure 21. Equivalent Circuit for Figure 15 During Common Mode Transient.
The open collector drive circuit, shown in Figure 22, can
not keep the LED off during a +dV
all the current flowing through C
by the LED, and it is not recommended for applications
requiring ultra high CMR
drive circuit which like the recommended application
circuit (Figure 17), does achieve ultra high CMR perfor-
mance by shunting the LED in the off state.
Figure 22. Not Recommended Open Collector Drive Circuit.
Figure 23. Recommended LED Drive Circuit for Ultra-High CMR Dead Time
and Propagation Delay Specifications.
+ 5 V
SAT
+5 V
+5 V
+5 V
+5 V
F(OFF)
Q1
Q1
Q1
of the logic gate. As long as the low state voltage de-
) during common mode transients. For example,
1
1
2
2
3
3
+
+
+
-
-
-
V
V
V
SAT
SAT
SAT
1
1
2
2
3
3
C
C
C
C
CM
LEDP
LEDP
LEDN
LEDN
I
I
LEDN
LEDN
C
C
1
2
3
·
LEDP
LEDP
/dt transient in Figure 21, the current
·
THE ARROWS INDICATE THE DIRECTION
C
C
OF CURRENT FLOW DURING - dV
LEDN
LEDN
LEDP
C
C
SHIELD
LEDP
LEDN
I
I
LEDP
SHIELD
SHIELD
also flows through the R
SHIELD
L
L
)
V
performance. The alternative
CM
LEDN
CM
CM
6
6
5
5
4
4
/ dt
/dt transient, since
6
6
5
5
4
4
must be supplied
0.1 mF
6
5
4
F(OFF)
+
+
-
-
V
the LED
SAT
CC
= 18V
R
g
and
F