PN5120A0HN/C1,557 NXP Semiconductors, PN5120A0HN/C1,557 Datasheet - Page 48

• Manufacturer Part Number: PN5120A0HN/C1,557
• Description: IC TRANSMISSION MOD 40-HVQFN
• Manufacturer: NXP Semiconductors

Specifications of PN5120A0HN/C1,557

• Rf Type: Read / Write
• Frequency: 13.56MHz
• Features: ISO14443-A, ISO14443-B
• Package / Case: 40-VFQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

NXP Semiconductors
PN512
Product data sheet
COMPANY PUBLIC
9.2.3.1 PageReg
9.2.3.2 CRCResultReg
9.2.3 Page 2: Configuration
Selects the register page.
Table 78.
Table 79.
Shows the actual MSB and LSB values of the CRC calculation.
Note: The CRC is split into two 8-bit register.
Note: Setting the bit MSBFirst in ModeReg register reverses the bit order, the byte order is
not changed.
Table 80.
Table 81.
Table 82.
Table 83.
Bit
7
6 to 2
1 to 0
Bit
7 to 0
Bit
7 to 0
Access Rights
Access Rights
Access Rights
Symbol
UsePageSelect Set to logic 1, the value of PageSelect is used as register address A5
-
PageSelect
Symbol
CRCResultMSB
Symbol
CRCResultLSB
PageReg register (address 20h); reset value: 00h, 00000000b
Description of PageReg bits
CRCResultReg register (address 21h); reset value: FFh, 11111111b
Description of CRCResultReg bits
CRCResultReg register (address 22h); reset value: FFh, 11111111b
Description of CRCResultReg bits
All information provided in this document is subject to legal disclaimers.
UsePageSelect
7
7
r
r
r/w
7
Rev. 3.6 — 10 March 2011
Description
and A4. The LSB-bits of the register address are defined by the
address pins or the internal address latch, respectively.
Set to logic 0, the whole content of the internal address latch defines
the register address. The address pins are used as described in
Section 10.1 “Automatic microcontroller interface
Reserved for future use.
The value of PageSelect is used only if UsePageSelect is set to
logic 1. In this case, it specifies the register page (which is A5 and
A4of the register address).
Description
This register shows the actual value of the least significant byte of
the CRCResult register. It is valid only if bit CRCReady in register
Status1Reg is set to logic 1.
Description
This register shows the actual value of the most significant byte of
the CRCResultReg register. It is valid only if bit CRCReady in
register Status1Reg is set to logic 1.
6
6
r
r
111336
RFU
6
0
5
5
r
r
RFU
0
5
CRCResultMSB
CRCResultLSB
4
4
r
r
RFU
4
0
3
3
r
r
RFU
3
0
2
2
r
r
Transmission module
RFU
2
0
detection”.
© NXP B.V. 2011. All rights reserved.
1
1
r
r
PN512
r/w
PageSelect
1
48 of 125
r/w
0
0
r
r
0