CS495303-CVZ Cirrus Logic Inc, CS495303-CVZ Datasheet - Page 24

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CS495303-CVZ

Manufacturer Part Number
CS495303-CVZ
Description
IC, AUDIO DECODER DSP, LQFP-128
Manufacturer
Cirrus Logic Inc
Datasheet

Specifications of CS495303-CVZ

Audio Control Type
Decoder
Control Interface
I2C, Parallel, SPI, UART
Control / Process Application
DVD AV Player, Audio Decoder, Audio Post-Processor, Audio Encoder
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CS495303-CVZ
Manufacturer:
CIRRUS LOGIC
Quantity:
200
CS4953xx Data Sheet
32-bit Audio Decoder DSP Family
5.18 Switching Characteristics — DSD Slave Input Port
5.19 Switching Characteristics — Digital Audio Output Port
24
DSD_SCLK Pulse Width Low
DSD_SCLK Pulse Width High
DSD_SCLK Frequency
DSD_A / _B valid to DSD_SCLK rising setup time
DSD_SCLK rising to DSD_A or DSD_B hold time
DSD clock to data transition (Phase Modulation mode)
DAO_MCLK period
DAO_MCLK duty cycle
DAO_SCLK period for Master or Slave mode
DAO_SCLK duty cycle for Master or Slave mode
Master Mode (Output A1 Mode)
DAO_SCLK delay from DAO_MCLK rising edge, DAO_MCLK as an
input
DAO_LRCLK delay from DAO_SCLK transition, respectively
DAO_DATA[3:0] delay from DAO_SCLK transition
Slave Mode (Output A0 Mode)
DAO_DATA[3..0] delay from DAO_SCLK transition
1. CS4953xx has two Digital Audio Output modules having similar signal names ending in 1 and 2. Both DAO ports
2. Master mode timing specifications are characterized, not production tested.
3. Master mode is defined as the CS4953xx driving both DAO_SCLK, DAO_LRCLK. When MCLK is an input, it is
4. This timing parameter is defined from the non-active edge of DAO_SCLK. The active edge of DAO_SCLK is the
5.Slave mode is defined as DAO_SCLK, DAO_LRCLK driven by an external source.
share a common MCLK but have independent SCLKs and LRCLKs.
divided to produce DAO_SCLK, DAO_LRCLK.
point at which the data is valid.
1
1
Parameter
Parameter
5
Figure 13. Direct Stream Digital - Serial Audio Input Timing
2,3
2
®Copyright 2008 Cirrus Logic, Inc.
(64x Oversampled)
2
4
4
4
Symbol
t
t
t
t
sclkh
t
sdlrs
sclkl
dpm
sdh
-
Symbol
T
t
t
T
t
daomsck
daomstlr
t
daomdv
daomclk
daosdv
daosclk
-
-
1.024
Min
-20
78
78
20
20
Min
40
40
40
40
-
-
-
Typ
-
-
-
-
-
-
Max
Max
3.2
20
60
60
19
10
15
8
-
-
-
-
-
-
DS705PP2
Unit
MHz
ns
ns
ns
ns
ns
Unit
ns
ns
ns
ns
ns
ns
%
%

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