XCF01SVOG20C Xilinx Inc, XCF01SVOG20C Datasheet - Page 23

• Manufacturer Part Number: XCF01SVOG20C
• Description: INTERGRATED CIRCUIT
• Manufacturer: Xilinx Inc

Specifications of XCF01SVOG20C

• Programmable Type: In System Programmable
• Memory Size: 1Mb
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-TSSOP (0.173", 4.40mm Width)
• Memory Type: Flash
• Interface Type: Serial, Parallel, JTAG
• Clock Frequency: 50MHz
• Supply Voltage Range: 2.3V To 2.7V, 3V To 3.6V
• Memory Case Style: TSSOP
• No. Of Pins: 20
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 122-1286-5

AC Characteristics Over Operating Conditions When Cascading
X-Ref Target - Figure 10
DS123 (v2.18) May 19, 2010
Product Specification
Notes:
1.
2.
3.
4.
5.
6.
T
T
T
T
T
T
CDF
OCK
OCE
OOE
COCE
CODF
Symbol
AC test load = 50 pF for XCF01S/XCF02S/XCF04S; 30 pF for XCF08P/XCF16P/XCF32P.
Float delays are measured with 5 pF AC loads. Transition is measured at ±200 mV from steady state active levels.
Guaranteed by design, not tested.
All AC parameters are measured with V
For cascaded PROMs, if the FPGA’s dual-purpose configuration data pins are set to persist as configuration pins, the minimum period is
increased based on the CLK to CEO and CE to data propagation delays:
- T
- T
For cascaded PROMs, if the FPGA’s dual-purpose configuration data pins become general I/O pins after configuration; to allow for the
disable to propagate to the cascaded PROMs and to avoid contention on the data lines following configuration, the minimum period is
increased based on the CE to CEO and CE to data propagation delays:
- T
- T
CYC
CAC
CYC
CAC
minimum = T
maximum = T
minimum = T
maximum = T
OE/RESET
R
CLK to output float delay
when V
CLK to output float delay
CLK to CEO delay
CLK to CEO delay
CE to CEO delay
CE to CEO delay
OE/RESET to CEO delay
OE/RESET to CEO delay
CLKOUT to CEO delay when V
CLKOUT to CEO delay when V
CLKOUT to output float delay
when V
CLKOUT to output float delay when V
(optional)
CLKOUT
DATA
CEO
CLK
CE
CCO
CCO
OCK
OCE
OCK
OCK
= 2.5V or 3.3V
= 2.5V or 3.3V
+ T
+ T
+ T
+ T
CE
CE
(3,6)
(3,6)
CE
CE
(3,5)
(3,5)
+ FPGA Data setup time
Description
when V
when V
when V
when V
(2,3)
(2,3)
(3)
(3)
IL
when V
when V
when V
CCO
CCO
Last Bit
= 0.0V and V
CCO
CCO
CCO
CCO
= 2.5V or 3.3V
= 1.8V
= 2.5V or 3.3V
= 1.8V
= 2.5V or 3.3V
= 1.8V
CCO
CCO
CCO
CCO
= 2.5V or 3.3V
= 1.8V
= 1.8V
= 1.8V
IH
= 3.0V.
www.xilinx.com
Platform Flash In-System Programmable Configuration PROMs
T
T
T
T
CDF
CODF
OCK
COCE
XCF01S, XCF02S,
Min
–
–
–
–
–
–
–
–
–
–
–
–
XCF04S
Max
25
35
20
35
20
35
20
35
–
–
–
–
T
T
OCE
OOE
XCF08P, XCF16P,
Min
–
–
–
–
–
–
–
–
–
–
–
–
XCF32P
ds123_23_102203
First Bit
Max
20
20
20
20
80
80
80
80
20
20
25
25
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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