AD724JR Analog Devices Inc, AD724JR Datasheet - Page 4

• Manufacturer Part Number: AD724JR
• Description: TV / Video IC
• Manufacturer: Analog Devices Inc
• Type: Video Encoderr

Specifications of AD724JR

• No. Of Pins: 16
• Peak Reflow Compatible (260 C): No
• Leaded Process Compatible: No
• Package / Case: 16-SOIC
• Rohs Status: RoHS non-compliant
• Applications: RGB To NTSC/PAL
• Voltage - Supply, Digital: 4.75 V ~ 5.25 V
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Voltage - Supply, Analog: -
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

AD724
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
*The Luminance, Chrominance and Composite Outputs are at twice normal levels for driving 75
Mnemonic
STND
AGND
FIN
APOS
ENCD
RIN
GIN
BIN
CRMA
COMP
LUMA
SELECT
DGND
DPOS
VSYNC
HSYNC
Description
A Logical HIGH input selects NTSC encoding.
A Logical LOW input selects PAL encoding.
CMOS/TTL Logic Levels.
Analog Ground Connection.
FSC clock or parallel-resonant crystal, or 4FSC clock input.
For NTSC: 3.579 545 MHz or 14.318 180 MHz.
For PAL: 4.433 619 MHz or 17.734 480 MHz.
CMOS/TTL Logic Levels for subcarrier clocks.
Analog Positive Supply (+5 V
A Logical HIGH input enables the encode function.
A Logical LOW input powers down chip when not in use.
CMOS/TTL Logic Levels.
Red Component Video Input.
0 to 714 mV AC-Coupled.
Green Component Video Input.
0 to 714 mV AC-Coupled.
Blue Component Video Input.
0 to 714 mV AC-Coupled.
Chrominance Output.*
Approximately 1.8 V peak-to-peak for both NTSC and PAL.
Composite Video Output.*
Approximately 2.5 V peak-to-peak for both NTSC and PAL.
Luminance plus SYNC Output.*
Approximately 2 V peak-to-peak for both NTSC and PAL.
A Logical LOW input selects the FSC operating mode.
A Logical HIGH input selects the 4FSC operating mode.
CMOS/TTL Logic Levels.
Digital Ground Connections.
Digital Positive Supply (+5 V
Vertical Sync Signal (if using external CSYNC set at > +2 V). CMOS/TTL Logic Levels.
Horizontal Sync Signal (or CSYNC signal). CMOS/TTL Logic Levels.
12
15
16
1
5
3
DGND
DPOS
DPOS
DGND
Circuit A
Circuit B
V
PIN FUNCTION DESCRIPTIONS
BIAS
5%).
5%).
Equivalent Circuits
–4–
6
7
8
DGND
DPOS
reverse-terminated lines.
AGND
APOS
Circuit C
Circuit D
DGND
DPOS
V
CLAMP
10
11
9
Equivalent Circuit
Circuit A
Circuit B
Circuit A
Circuit C
Circuit C
Circuit C
Circuit D
Circuit D
Circuit D
Circuit A
Circuit A
Circuit A
REV. B