AD808-622BRZ Analog Devices Inc, AD808-622BRZ Datasheet - Page 5

• Manufacturer Part Number: AD808-622BRZ
• Description: Fiber Optic Receiver - 622 Mbps
• Manufacturer: Analog Devices Inc
• Type: Receiverr

Specifications of AD808-622BRZ

• Voltage - Supply: 4.5 V ~ 5.5 V
• Mounting Type: Surface Mount
• Package / Case: 16-SOIC (3.9mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Drivers/receivers: -
• Protocol: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

REV. 0
Damping Factor,
Damping factor, describes the compensation of the second
order PLL. A larger value of corresponds to more damping
and less peaking in the jitter transfer function.
Acquisition Time
This is the transient time, measured in bit periods, required for
the AD808 to lock onto input data from its free-running state.
Symmetry—Recovered Clock Duty Cycle
Symmetry is calculated as (100 on time)/period, where on
time equals the time that the clock signal is greater than the
midpoint between its “0” level and its “1” level.
The AD808 has internal circuits to set the common-mode volt-
age at the quantizer inputs PIN (Pin 13) and NIN (Pin 12) as
shown in Figure 4a. This allows very simple capacitive coupling
of the signal from the preamp in the AD808 as shown in Figure
3. The internal common-mode potential is a diode drop (ap-
proximately 0.8 V) below the positive supply as shown in Figure
4a. Since the common mode is referred to the positive supply, it
Figure 3. (a–b) Single-Ended and Differential Input
Applications
–INPUT
+INPUT
INPUT
a. Single-Ended Input Application
b. Differential Input Application
V
CM
V
V
CM
CM
V
SCOPE
PROBE
CM
SCOPE
PROBE
AD808 QUANTIZER
AD808 QUANTIZER
4mVp-p
2mVp-p
BINARY
OUTPUT
BINARY
OUTPUT
–5–
is useful to bypass the common mode of the preamp to the
positive supply as well, if this is an option. Note, it is not neces-
sary to use capacitive coupling of the input signal with the
AD808. Figure 14 shows the input common-mode voltage can
be externally set.
d. PLL Differential Output Stage—DATAOUT(N),
PIN
NIN
CLKOUT(N)
Figure 4. (a–d) Simplified Schematics
5k
5k
a. Quantizer Differential Input Stage
c. Signal Detect Output (SDOUT)
140
7.8mA
1.2V +V
BE
b. Threshold Adjust
I
I
OH
OL
140
AV
AV
CC
EE
6k
80k
30
30
500
THRADJ
AV
OUT
V
DIFFERENTIAL
OUTPUT
V
EE
CC2
EE
V
SDOUT
V
CC1
EE
500
AD808