AD9233-125EBZ Analog Devices Inc, AD9233-125EBZ Datasheet
AD9233-125EBZ
Specifications of AD9233-125EBZ
Related parts for AD9233-125EBZ
AD9233-125EBZ Summary of contents
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... Battery-powered instruments Hand-held scopemeters Low cost digital oscilloscopes GENERAL DESCRIPTION The AD9233 is a monolithic, single 1.8 V supply, 12-bit, 80 MSPS/ 105 MSPS/125 MSPS analog-to-digital converter (ADC), featuring a high performance sample-and-hold amplifier (SHA) and on- chip voltage reference. The product uses a multistage differential pipeline architecture with output error correction logic to provide 12-bit accuracy at 125 MSPS data rates and guarantees no missing codes over the full operating temperature range ...
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... AD9233 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Product Highlights ........................................................................... 1 Revision History ............................................................................... 3 Specifications..................................................................................... 4 DC Specifications ......................................................................... 4 AC Specifications.......................................................................... 5 Digital Specifications ................................................................... 6 Switching Specifications .............................................................. 7 Timing Diagram ........................................................................... 7 Absolute Maximum Ratings............................................................ 8 Thermal Resistance ...................................................................... 8 ESD Caution.................................................................................. 8 Pin Configuration and Function Descriptions............................. 9 Equivalent Circuits ......................................................................... 10 Typical Performance Characteristics ........................................... 11 Theory of Operation ...
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... Changes to Digital Outputs Section .............................................21 Changes to Timing Section............................................................22 Added Data Clock Output (DCO) Section..................................22 Changes to Configuration Using the SPI Section and Configuration Without the SPI Section .......................................23 Changes to Table 15 ........................................................................25 Changes to Table 16 ........................................................................39 Changes to Ordering Guide...........................................................42 4/06—Revision 0: Initial Version Rev Page AD9233 ...
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... Full 138 155 Full 7 Full 12 Full 248 279 Full 261 Full 288 Full 40 Full 1.8 Rev Page AD9233BCPZ-125 Typ Max Min Typ Max 12 Guaranteed Guaranteed ±0.3 ±0.8 ±0.3 ±0.8 ±0.2 ±4.9 ±0.2 ±3.9 ±0.5 ±0.5 ±0.2 ±0.2 ±1.2 ± ...
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... Full −85.0 25°C −90.0 25°C −90.0 25°C 87 25°C 83 25°C 650 Rev Page AD9233 AD9233BCPZ-125 Typ Max Min Typ Max 69.5 69.5 69.5 69.5 68.3 69.4 69.4 68.9 68.9 69.2 69.2 69.2 69.2 67.3 69 ...
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... Full Full Full Full Full Full Full Full = 50 μA) Full = 0.5 mA) Full Full Full = 50 μA) Full = 0.5 mA) Full Full Full Rev Page AD9233BCPZ-80/105/125 Min Typ Max CMOS/LVDS/LVPECL 1.2 0.2 6 AVDD − 0.3 AVDD + 1.6 1.1 AVDD 1.2 3.6 0 0.8 −10 +10 −10 +10 8 ...
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... – – – – CLK AD9233 Max Unit 125 MSPS 125 MSPS ns 5.6 ns 4 cycles ns ps rms ms cycles ...
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... AD9233 ABSOLUTE MAXIMUM RATINGS Table 5. Parameter Rating ELECTRICAL AVDD to AGND −0 +2.0 V DRVDD to DRGND −0 +3.9 V AGND to DRGND −0 +0.3 V AVDD to DRVDD −3 +2 through D11 to DRGND −0 DRVDD + 0.3 V DCO to DRGND −0 DRVDD + 0 DRGND −0 DRVDD + 0.3 V CLK+ to AGND −0 +3.9 V CLK− ...
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... Common-Mode Level Bias Output. External Bias Resister Connection kΩ resister must be connected between this pin and analog ground (AGND). Power-Down Function Select. Clock Input (+). Clock Input (−). Output Enable (Active Low). Data Clock Output. No Connection. Rev Page AD9233 36 PDWN 35 RBIAS 34 CML 33 AVDD 32 ...
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... AD9233 EQUIVALENT CIRCUITS VIN Figure 4. Equivalent Analog Input Circuit AVDD 1.2V 10kΩ 10kΩ CLK+ Figure 5. Equivalent Clock Input Circuit DRVDD 1kΩ SDIO/DCS Figure 6. Equivalent SDIO/DCS Input Circuit DRVDD DRGND Figure 7. Equivalent Digital Output Circuit SCLK/DFS OEB PDWN Figure 8. Equivalent SCLK/DFS, OEB, PDWN Input Circuit CSB CLK– ...
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... Figure 15. AD9233-125 Single-Tone FFT with F = 2.3 MHz IN 0 –20 –40 –60 –80 –100 –120 –140 46.875 62.500 Figure 16. AD9233-125 Single-Tone FFT with F = 30.3 MHz IN 0 –20 –40 –60 –80 –100 –120 –140 46.875 62.500 = 70.3 MHz Figure 17. AD9233-125 Single-Tone FFT with F IN Rev ...
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... Figure 22. AD9233 Single-Tone SNR/SFDR vs. Input Frequency (F ) and Temperature with 1 V p-p Full Scale IN 1.0 0.8 OFFSET ERROR 0.5 0.3 0 GAIN ERROR –0.3 –0.5 –0.8 –1.0 – –40 TEMPERATURE (°C) Figure 23. AD9233 Gain and Offset vs. Temperature SFDR = +25°C 200 250 SFDR = +25°C 200 250 60 80 ...
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... FREQUENCY (MHz) Figure 24. AD9233-125 Two-Tone FFT with F IN1 0 125MSPS 169.1MHz @ –7dBFS –20 172.1MHz @ –7dBFS SFDR = 84dBc (91dBFS) –40 –60 –80 –100 –120 –140 0 15.625 31.250 FREQUENCY (MHz) Figure 25. AD9233-125 Two-Tone FFT with F = 169 ...
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... CLOCK FREQUENCY (MSPS) Figure 30. AD9233 Single-Tone SNR/SFDR vs. Clock Frequency (F ) with 100 SFDR DCS = ON 90 SFDR DCS = OFF DUTY CYCLE (%) Figure 31. AD9233 SNR/SFDR vs. Duty Cycle with F 90 SFDR SNR 65 0.5 0.7 0.9 INPUT COMMON-MODE VOLTAGE (V) Figure 32. AD9233 SNR/SFDR vs. Input Common Mode (V ) with ...
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... ADC. The output common-mode voltage of the AD8138 is easily set with the CML pin of the AD9233 (see Figure 37), and the driver can be configured in a Sallen-Key filter topology to provide band limiting of the input signal. Rev Page AD9233 ...
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... ANALOG INPUT At input frequencies in the second Nyquist zone and above, the noise performance of most amplifiers is not adequate to achieve VIN+ the true SNR performance of the AD9233. For applications AVDD where SNR is a key parameter, transformer coupling is the AD9233 recommended input. For applications where SFDR is a key ...
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... ADC AD9233 VIN– 0.1µF 0.1µF If the internal reference of the AD9233 is used to drive multiple converters to improve gain matching, the loading of the reference by the other converters must be considered. Figure 44 depicts how the internal reference voltage is affected by loading. Rev Page ⎛ + ⎞ ...
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... AD9233 to approximately 0.8 V p-p differential. This helps prevent the large voltage swings of the clock from feeding through to other portions of the AD9233 while preserving the fast rise and fall times of the signal, which are critical to a low jitter performance. CLOCK ...
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... Commonly, a ±5% tolerance is required on the clock duty cycle to maintain dynamic perform- ance characteristics. The AD9233 contains a DCS that retimes the nonsampling, or falling edge, providing an internal clock signal with a nominal 50% duty cycle. This allows a wide range of clock input duty cycles without affecting the performance of the AD9233 ...
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... ADCs. POWER DISSIPATION AND STANDBY MODE As shown in Figure 52 and Figure 53, the power dissipated by the AD9233 is proportional to its sample rate. The digital power dissipation is determined primarily by the strength of the digital drivers and the load on each output bit. The maximum DRVDD ...
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... Digital Output Enable Function (OEB) Manual, the The AD9233 has three-state ability. If the OEB pin is low, the output data drivers are enabled. If the OEB pin is high, the output data drivers are placed in a high impedance state. This is not intended for rapid access to the data bus. Note that OEB is referenced to the digital supplies (DRVDD) and should not exceed that supply voltage ...
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... AD9233 TIMING The lowest typical conversion rate of the AD9233 is 10 MSPS. At clock rates below 10 MSPS, dynamic performance can degrade. The AD9233 provides latched data outputs with a pipeline delay of 12 clock cycles. Data outputs are available one propagation delay (t ) after the rising edge of the clock signal. ...
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... SERIAL PORT INTERFACE (SPI) The AD9233 SPI allows the user to configure the converter for specific functions or operations through a structured register space provided inside the ADC. This provides the user added flexibility and customization depending on the application. Addresses are accessed via the serial port and can be written to or read from via the port ...
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... AD9233 MEMORY MAP READING THE MEMORY MAP TABLE Each row in the memory map table has eight address locations. The memory map is roughly divided into three sections: chip configuration registers map (Address 0x00 to Address 0x02), device index and transfer registers map (Address 0xFF), and ADC functions map (Address 0x08 to Address 0x18) ...
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... Flexible ADC Functions 10 offset Bit 5 Bit 4 Bit 3 Bit 2 Soft 1 1 Soft Reset Reset 0 = Off 0 = Off (Default) (Default 8-Bit Chip ID Bits 7:0 (AD9233 = 0x00), (Default) Open Open Child ID Open 0 = 125 MSPS 105 MSPS Open Open Open Open PDWN Open Open Internal Power-Down Mode 0—Full 000— ...
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... AD9233 Addr Parameter Bit 7 (Hex) Name (MSB) Bit 6 0D test_io 14 output_mode Output Driver Configuration 00 for DRVDD = 3 for DRVDD = 1 output_phase DCO Open Polarity 1 = Inverted 0 = Normal 18 VREF Internal Reference Resistor Divider 00—VREF = 1.25 V 01—VREF = 1.5 V 10—VREF = 1.75 V 11—VREF = 2. External Output Enable (OEB) pin must be high. ...
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... The CML pin should be decoupled to ground with a 0.1 μF capacitor, as shown in Figure 38. RBIAS The AD9233 requires the user to place a 10 kΩ resistor between the RBIAS pin and ground. This resister sets the master current reference of the ADC core and should have at least a 1% tolerance. ...
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... Figure 59 shows the typical bench characterization setup used to evaluate the ac performance of the AD9233 critical that the signal sources used for the analog input and clock have very low phase noise (<1 ps rms jitter) to realize the optimum performance of the converter ...
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... DEFAULT OPERATION AND JUMPER SELECTION SETTINGS The following is a list of the default and optional settings or modes allowed on the AD9233 Rev. A evaluation board. POWER Connect the switching power supply that is supplied in the evaluation kit between a rated 100 240 V ac wall outlet and P500. ...
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... AD9233 ALTERNATIVE ANALOG INPUT DRIVE CONFIGURATION This section provides a brief description of the alternative analog input drive configuration using the using this particular drive option, some components need to be populated as listed in Table 16. For more details on the differential driver, including how it works and its optional pin ...
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... SCHEMATICS RC0402 RC0402 RC040 2 RC040 2 RC0402 CC0402 2 HSMS281 2 HSMS281 RC0402 CC0402 CC0402 RC060 3 RC060 3 Figure 60. Evaluation Board Schematic, DUT Analog Inputs Rev Page AD9233 05492-058 CC0402 RC060 3 RC060 3 ...
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... AD9233 Figure 61. Evaluation Board Schematic, DUT, VREF, and Digital Output Interface RC060 3 Rev Page 05492-059 ...
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... CC0402 CC0402 RC0402 RC060 3 CC0402 CC0402 RC060 3 RC060 3 Figure 62. Evaluation Board Schematic, DUT Clock Inputs Rev Page CC0402 CC0402 CC0402 CC0402 RC0402 RC0402 RC0402 RC0402 S10 GND_PAD S10 S0 7 VREF 32 6 RSET RC0402 RC0402 RC0402 RC0402 RC0402 RC0402 AD9233 05492-057 ...
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... AD9233 RC0603 SDO_CH A RC0603 CSB1_CHA RC0603 SDI_CHA RC0603 SCLK_CH A RC0603 RC0603 RC0603 RC0603 RC0603 1 2 PICVCC PICVCC 3 4 GP1 GP1 5 6 GP0 GP0 7 8 MCLR-GP3 MC LR-GP3 RC060 Figure 63. Evaluation Board Schematic, SPI Circuitry Rev Page 05492-056 RC0603 ...
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... GND GND 1 1 GND GND GND CR500 1 2 Figure 64. Evaluation Board Schematic, Power Supply Inputs Rev Page AD9233 05492-055 TP509 TP512 TP511 TP510 ...
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... AD9233 EVALUATION BOARD LAYOUTS Figure 65. Evaluation Board Layout, Primary Side Figure 66. Evaluation Board Layout, Secondary Side (Mirrored Image) Rev Page ...
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... Figure 67. Evaluation Board Layout, Ground Plane Figure 68. Evaluation Board Layout, Power Plane Rev Page AD9233 ...
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... AD9233 Figure 70. Evaluation Board Layout, Silkscreen Secondary Side (Mirrored Image) Figure 69. Evaluation Board Layout, Silkscreen Primary Side Rev Page ...
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... Oscillator SMT 125 MHz or 105 MHz Connector PJ-102A DC power jack Connector 10 Pin Male, straight Rev Page AD9233 Supplier/Part No. Analog Devices, Inc. Panasonic LNJ314G8TRA HSMS2812 Micro Commercial Group SK33-TPMSCT-ND Micro Commercial Group S2A-TPMSTR-ND Amber LED Tyco, Raychem NANO SMDC110F-2 ...
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... AD9233 Omit Item Qty. (DNI) Reference Designator 29 6 R1, R6, R563, R565, R574, R577 30 5 R2, R5, R561, R562, R571 6 R10, R11, R12, R535, R536, R575 R7, R8, R9, R502, R510, R511 33 6 R500, R501, R576, R578, R579, R581 34 4 R503, R548, R549, R550 ...
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... IC SC70 Dual buffer IC SC70 Dual buffer IC 48-Lead Buffer/line driver TSSOP DUT 48-Lead ADC (AD9233) LFCSP IC 16-Lead Differential LFCSP amplifier Rev Page AD9233 Supplier/Part No. Microchip PIC12F629 Fairchild NC7WZ16 Fairchild NC7WZ07 Fairchild 74VCX162244 Analog Devices, Inc. AD9233BCPZ Analog Devices, Inc. AD8352ACPZ ...
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... AD9233BCPZRL7–105 –40°C to +85°C 2 AD9233BCPZ-80 –40°C to +85°C 2 AD9233BCPZRL7–80 –40°C to +85°C AD9233-125EB AD9233-105EB AD9233-80EB required that the exposed paddle be soldered to the AGND plane to achieve the best electrical and thermal performance . Pb-free part. ...
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... NOTES Rev Page AD9233 ...
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... AD9233 NOTES ©2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05492-0-8/06(A) Rev Page ...