AD9238BSTZ-40 Analog Devices Inc, AD9238BSTZ-40 Datasheet - Page 4

IC,A/D CONVERTER,DUAL,12-BIT,CMOS,QFP,64PIN

AD9238BSTZ-40

Manufacturer Part Number
AD9238BSTZ-40
Description
IC,A/D CONVERTER,DUAL,12-BIT,CMOS,QFP,64PIN
Manufacturer
Analog Devices Inc
Datasheet

Specifications of AD9238BSTZ-40

Rohs Compliant
YES
Number Of Bits
12
Sampling Rate (per Second)
40M
Data Interface
Parallel
Number Of Converters
2
Power Dissipation (max)
330mW
Voltage Supply Source
Single Supply
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
64-LQFP
Number Of Elements
2
Resolution
12Bit
Architecture
Pipelined
Sample Rate
40MSPS
Input Polarity
Unipolar
Input Type
Voltage
Rated Input Volt
±0.5/±1V
Differential Input
Yes
Power Supply Requirement
Single
Single Supply Voltage (typ)
3V
Single Supply Voltage (min)
2.7V
Single Supply Voltage (max)
3.6V
Dual Supply Voltage (typ)
Not RequiredV
Dual Supply Voltage (min)
Not RequiredV
Dual Supply Voltage (max)
Not RequiredV
Power Dissipation
397mW
Differential Linearity Error
±0.8LSB
Integral Nonlinearity Error
±1.4LSB
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
64
Package Type
LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AD9238BCP-65EBZ - BOARD EVAL WITH AD9238BCP-65AD9238BCP-40EBZ - BOARD EVAL WITH AD9238BCP-40
Lead Free Status / Rohs Status
Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AD9238BSTZ-40
Manufacturer:
ADI
Quantity:
300
Part Number:
AD9238BSTZ-40
Manufacturer:
Analog Devices Inc
Quantity:
10 000
Part Number:
AD9238BSTZ-40
Manufacturer:
ADI/亚德诺
Quantity:
20 000
AD9238
SPECIFICATIONS
DC SPECIFICATIONS
AVDD = 3 V, DRVDD = 2.5 V, maximum sample rate, CLK_A = CLK_B; A
T
Table 1.
Parameter
RESOLUTION
ACCURACY
TEMPERATURE DRIFT
INTERNAL VOLTAGE REFERENCE
INPUT REFERRED NOISE
ANALOG INPUT
REFERENCE INPUT RESISTANCE
POWER SUPPLIES
POWER CONSUMPTION
MATCHING CHARACTERISTICS
1
2
3
4
5
Gain error and gain temperature coefficient are based on the ADC only (with a fixed 1.0 V external reference).
Measured at maximum clock rate with a low frequency sine wave input and approximately 5 pF loading on each output bit.
Input capacitance refers to the effective capacitance between one differential input pin and AVSS. Refer to Figure
Measured with dc input at maximum clock rate.
Standby power is measured with the CLK_A and CLK_B pins inactive (that is, set to AVDD or AGND).
MIN
No Missing Codes Guaranteed
Offset Error
Gain Error
Differential Nonlinearity (DNL)
Integral Nonlinearity (INL)
Offset Error
Gain Error
Output Voltage Error (1 V Mode)
Load Regulation @ 1.0 mA
Output Voltage Error (0.5 V Mode)
Load Regulation @ 0.5 mA
Input Span = 1 V
Input Span = 2.0 V
Input Span = 1.0 V
Input Span = 2.0 V
Input Capacitance
Supply Voltages
Supply Current
PSRR
DC Input
Sine Wave Input
Standby Power
Offset Error
Gain Error
AVDD
DRVDD
IAVDD
IDRVDD
to T
MAX
2
4
, DCS enabled, unless otherwise noted.
1
2
5
2
3
2
2
Temp
Full
Full
Full
Full
Full
25°C
Full
25°C
Full
Full
Full
Full
Full
Full
25°C
25°C
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
25°C
25°C
Test
Level
VI
VI
VI
IV
V
I
V
I
V
V
VI
V
V
V
V
V
IV
IV
V
V
IV
IV
V
V
V
V
VI
V
V
V
Min
12
12
2.7
2.25
AD9238BST/BCP-20
Rev. C | Page 4 of 48
Typ
±0.30
±0.30
±0.35
±0.35
±0.45
±0.40
±4
±12
±5
0.8
±2.5
0.1
0.54
0.27
1
2
7
7
3.0
3.0
60
4
±0.01
180
190
2.0
±0.1
±0.05
Max
±1.2
±2.2
±0.9
±1.4
±35
3.6
3.6
212
IN
= −0.5 dBFS differential input, 1.0 V internal reference,
Min
12
12
2.7
2.25
AD9238BST/BCP-40
Typ
±0.50
±0.50
±0.35
±0.35
±0.60
±0.50
±4
±12
±5
0.8
±2.5
0.1
0.54
0.27
1
2
7
7
3.0
3.0
110
10
±0.01
330
360
2.0
±0.1
±0.05
29
for the equivalent analog input structure.
Max
±1.1
±2.4
±0.8
±1.4
±35
3.6
3.6
397
Min
12
12
2.7
2.25
AD9238BST/BCP-65
Typ
±0.50
±0.50
±0.35
±0.35
±0.70
±0.55
±6
±12
±5
0.8
±2.5
0.1
0.54
0.27
1
2
7
7
3.0
3.0
200
14
±0.01
600
640
2.0
±0.1
±0.05
±2.5
±1.0
3.6
698
Max
±1.1
±1.75
±35
3.6
Unit
Bits
Bits
% FSR
% FSR
LSB
LSB
LSB
LSB
μV/°C
ppm/°C
mV
mV
mV
mV
LSB rms
LSB rms
V p-p
V p-p
pF
V
V
mA
mA
% FSR
mW
mW
mW
% FSR
% FSR

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