AD9245BCPZ-65 Analog Devices Inc, AD9245BCPZ-65 Datasheet - Page 20

• Manufacturer Part Number: AD9245BCPZ-65
• Description: IC,A/D CONVERTER,SINGLE,14-BIT,CMOS,LLCC,32PIN
• Manufacturer: Analog Devices Inc

Specifications of AD9245BCPZ-65

• Number Of Bits: 14
• Sampling Rate (per Second): 65M
• Data Interface: Parallel
• Number Of Converters: 3
• Power Dissipation (max): 300mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 32-VFQFN, CSP Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AD9245BCP-80EBZ - BOARD EVAL FOR AD9245BCP-80AD9245BCP-40EBZ - BOARD EVAL FOR AD9245BCP-40AD9245BCP-20EBZ - BOARD EVAL FOR AD9245BCP-20
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9245
JITTER CONSIDERATIONS
High speed, high resolution ADCs are sensitive to the quality
of the clock input. The degradation in SNR at a given input
frequency (f
calculated with the following equation:
In the equation, the rms aperture jitter represents the root-
mean square of all jitter sources, which include the clock input,
analog input signal, and ADC aperture jitter specification. IF
undersampling applications are particularly sensitive to jitter
(see Figure 43).
The clock input should be treated as an analog signal in cases
where aperture jitter can affect the dynamic range of the
AD9245. Power supplies for clock drivers should be separated
from the ADC output driver supplies to avoid modulating the
clock signal with digital noise. Low jitter, crystal-controlled
oscillators make the best clock sources. If the clock is generated
from another type of source (by gating, dividing, or other
methods), it should be retimed by the original clock at the last step.
POWER DISSIPATION AND STANDBY MODE
As shown in Figure 44, the power dissipated by the AD9245 is
proportional to its sample rate. The digital power dissipation is
determined primarily by the strength of the digital drivers and
the load on each output bit. The maximum DRVDD current
(I
where N is the number of output bits, 14 in the case of the
AD9245. This maximum current occurs when every output bit
switches on every clock cycle, that is, a full-scale square wave at
the Nyquist frequency, f
is established by the average number of output bits switching,
DRVDD
75
70
65
60
55
50
45
40
SNR = −20log
I
DRVDD
1
) can be calculated as
INPUT
=
Figure 43. SNR vs. Input Frequency and Jitter
V
) due only to aperture jitter (t
DRVDD
10
[2π f
INPUT FREQUENCY (MHz)
×
CLK
10
INPUT
C
/2. In practice, the DRVDD current
LOAD
× t
×
j
]
f
CLK
×
N
100
0.2ps
0.5ps
1.0ps
1.5ps
2.0ps
2.5ps
3.0ps
J
MEASURED SNR
) can be
1000
Rev. D | Page 20 of 32
which is determined by the sample rate and the characteristics
of the analog input signal.
Reducing the capacitive load presented to the output drivers can
minimize digital power consumption. The data in Figure 44 was
taken with the same operating conditions as those reported in
the Typical Performance Characteristics section, and with a
5 pF load on each output driver.
By asserting the PDWN pin high, the AD9245 is placed in
standby mode. In this state, the ADC typically dissipates
1 mW if the CLK and analog inputs are static. During standby,
the output drivers are placed in a high impedance state.
Reasserting the PDWN pin low returns the AD9245 to its
normal operational mode.
Low power dissipation in standby mode is achieved by shutting
down the reference, reference buffer, and biasing networks. The
decoupling capacitors on REFT and REFB are discharged when
entering standby mode and then must be recharged when
returning to normal operation. As a result, the wake-up time is
related to the time spent in standby mode, and shorter standby
cycles result in proportionally shorter wake-up times. With the
recommended 0.1 μF and 10 μF decoupling capacitors on REFT
and REFB, it takes approximately 1 second to fully discharge the
reference buffer decoupling capacitors and 7 ms to restore full
operation.
DIGITAL OUTPUTS
The AD9245 output drivers can be configured to interface with
2.5 V or 3.3 V logic families by matching DRVDD to the digital
supply of the interfaced logic. The output drivers are sized to
provide sufficient output current to drive a wide variety of logic
families. However, large drive currents tend to cause current
glitches on the supplies, which can affect converter performance.
Applications requiring the ADC to drive large capacitive loads or
large fanouts can require external buffers or latches.
450
400
350
300
250
200
150
100
50
0
AD9245-20
Figure 44. AD9245 Power vs. Sample Rate @ 2.5 MHz
10
AD9245-40
20
SAMPLE RATE (MSPS)
30
AD9245-65
40
AD9245-80
50
60
70
80