AD9518-1/PCBZ Analog Devices Inc, AD9518-1/PCBZ Datasheet
AD9518-1/PCBZ
Specifications of AD9518-1/PCBZ
Related parts for AD9518-1/PCBZ
AD9518-1/PCBZ Summary of contents
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... The AD9518-1 is specified for operation over the industrial range of −40°C to +85°C. 1 AD9518 is used throughout to refer to all the members of the AD9518 family. However, when AD9518-1 is used referring to that specific member of the AD9518 family. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. ...
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... AD9518-1 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 3 Specifications..................................................................................... 4 Power Supply Requirements ....................................................... 4 PLL Characteristics ...................................................................... 4 Clock Inputs .................................................................................. 6 Clock Outputs ............................................................................... 6 Timing Characteristics ................................................................ 7 Clock Output Additive Phase Noise (Distribution Only; VCO Divider Not Used) ........................................................................ 7 Clock Output Absolute Phase Noise (Internal VCO Used).... 8 Clock Output Absolute Time Jitter (Clock Generation Using Internal VCO) ...
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... Write .........................................................................................41 Read ..........................................................................................42 The Instruction Word (16 Bits).................................................42 MSB/LSB First Transfers ............................................................42 Register Map Overview ..................................................................45 REVISION HISTORY 9/07—Revision 0: Initial Version Register Map Descriptions.............................................................48 Application Notes............................................................................61 Using the AD9518 Outputs for ADC Clock Applications ....61 LVPECL Clock Distribution......................................................61 Outline Dimensions........................................................................62 Ordering Guide ...........................................................................62 Rev Page AD9518-1 ...
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... AD9518-1 SPECIFICATIONS Typical (typ) is given for 3.3 V ± 5 S_LVPECL unless otherwise noted. Minimum (min) and maximum (max) values are given over full V POWER SUPPLY REQUIREMENTS Table 1. Parameter Min Typ V 3.135 3 2.375 S_LVPECL RSET Pin Resistor 4.12 CPRSET Pin Resistor 5.1 BYPASS Pin Capacitor ...
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... Rev Page AD9518-1 Test Conditions/Comments Antibacklash pulse width = 1.3 ns, 2.9 ns Antibacklash pulse width = 6.0 ns 0x17<1:0> = 01b 0x17<1:0> = 00b; 0x17<1:0> = 11b 0x17<1:0> = 10b Programmable With CP = 5.1 kΩ RSET 0.5 < CP < ...
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... AD9518-1 Parameter 2 PLL DIGITAL LOCK DETECT WINDOW Required to Lock (Coincidence of Edges) Low Range (ABP 1.3 ns, 2.9 ns) High Range (ABP 1.3 ns, 2.9 ns) High Range (ABP 6 ns Unlock After Lock (Hysteresis) Low Range (ABP 1.3 ns, 2.9 ns) High Range (ABP 1.3 ns, 2.9 ns) High Range (ABP 6 ns) 1 REFIN and REFIN self-bias points are offset slightly to avoid chatter on an open input condition ...
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... Rev Page AD9518-1 − level = 810 mV S Test Conditions/Comments Distribution section only; does not include PLL and VCO Input slew rate > 1 V/ns Input slew rate > 1 V/ns ...
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... AD9518-1 CLOCK OUTPUT ABSOLUTE PHASE NOISE (INTERNAL VCO USED) Table 7. Parameter LVPECL ABSOLUTE PHASE NOISE VCO = 2.65 GHz; OUTPUT = 2.65 GHz @ 1 kHz Offset @ 10 kHz Offset @ 100 kHz Offset @ 1 MHz Offset @ 10 MHz Offset @ 40 MHz Offset VCO = 2.475 GHz; OUTPUT = 2.475 GHz @ 1 kHz Offset ...
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... Distribution section only; does not include PLL and VCO; uses rising edge of clock signal 210 fs rms Calculated from SNR of ADC method Rev Page AD9518-1 Test Conditions/Comments Application example based on a typical setup where the reference source is jittery narrower PLL loop bandwidth is used; reference = 10.0 MHz ...
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... AD9518-1 SERIAL CONTROL PORT Table 13. Parameter CS (INPUT) Input Logic 1 Voltage Input Logic 0 Voltage Input Logic 1 Current Input Logic 0 Current Input Capacitance SCLK (INPUT) Input Logic 1 Voltage Input Logic 0 Voltage Input Logic 1 Current Input Logic 0 Current Input Capacitance SDIO (WHEN INPUT) Input Logic 1 Voltage ...
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... All references off to REF1 or REF2 enabled; differential reference not enabled 70 mW CLK input selected to VCO selected 75 mW PLL off to PLL on, normal operation; no reference enabled 30 mW Divider bypassed to divide-by-2 to divide-by-32 160 mW No LVPECL output on to one LVPECL output Second LVPECL output turned on, same channel Rev Page AD9518-1 ...
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... AD9518-1 TIMING DIAGRAMS t CLK CLK t PECL Figure 2. CLK/ CLK to Clock Output Timing, DIV = 1 DIFFERENTIAL 80% 20 Figure 3. LVPECL Timing, Differential Rev Page LVPECL t FP ...
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... 0.3 V Package Type S −0 0.3 V 48-Lead LFCSP S 1 Thermal impedance measurements were taken on a 4-layer board in still air in accordance with EIA/JESD51-7. −0 0 −0 0 ESD CAUTION 150°C −65°C to +150°C 300°C Rev Page AD9518-1 1 θ Unit JA 28.5 °C/W ...
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... LVPECL Output; One Side of a Differential LVPECL Output. 39 OUT1 LVPECL Output; One Side of a Differential LVPECL Output. 38 OUT1 LVPECL Output; One Side of a Differential LVPECL Output. 1 PIN INDICATOR VCP STATUS 5 AD9518-1 6 TOP VIEW SYNC 7 (Not to Scale BYPASS CLK 11 CLK 12 Figure 4. Pin Configuration < V < ...
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... Along with REFIN, this is the differential input for the PLL reference. Alternatively, this pin is a single-ended input for REF2. 48 REFIN (REF1) Along with REFIN, this is the differential input for the PLL reference. Alternatively, this pin is a single-ended input for REF1 Connection. Rev Page AD9518-1 ...
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... AD9518-1 TYPICAL PERFORMANCE CHARACTERISTICS 300 3 CHANNELS—6 LVPECL 280 260 240 220 200 3 CHANNELS—3 LVPECL 180 160 2 CHANNELS—2 LVPECL 140 120 1 CHANNEL—1 LVPECL 100 0 500 1000 1500 FREQUENCY (MHz) Figure 5. Current vs. Frequency, Direct-to-Output, LVPECL Outputs 2.3 2.4 2.5 VCO FREQUENCY (GHz) Figure 6 ...
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... SPAN 50MHz 1600 1400 1200 1000 800 SPAN 1MHz Rev Page AD9518 TIME (ns) Figure 14. LVPECL Output (Differential) @ 100 MHz 0 1 TIME (ns) Figure 15. LVPECL Output (Differential) @ 1600 MHz FREQUENCY (GHz) Figure 16. LVPECL Differential Swing vs. Frequency ...
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... AD9518-1 –70 –80 –90 –100 –110 –120 –130 –140 –150 10k 100k 1M FREQUENCY (Hz) Figure 17. Internal VCO Phase Noise (Absolute) Direct to LVPECL @ 2650 MHz –70 –80 –90 –100 –110 –120 –130 –140 –150 10k 100k 1M FREQUENCY (Hz) Figure 18. Internal VCO Phase Noise (Absolute) Direct to LVPECL @ 2475 MHz – ...
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... PFD = 19.44 MHz; LBW = 12.8 kHz; LVPECL Output = 155.52 MHz –120 –130 –140 –150 –160 10M 100M 1k Figure 25. Phase Noise (Absolute); External VCXO (Toyocom TCO-2112) @ 245.76 MHz; PFD = 15.36 MHz; LBW = 250 Hz; LVPECL Output = 245.76 MHz 10M 100M Rev Page AD9518-1 10k 100k 1M 10M 100M FREQUENCY (Hz) ...
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... AD9518-1 TERMINOLOGY Phase Jitter and Phase Noise An ideal sine wave can be thought of as having a continuous and even progression of phase with time from 0° to 360° for each cycle. Actual signals, however, display a certain amount of variation from ideal phase progression over time. This phenomenon is called phase jitter ...
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... DIVIDER R DELAY VCO STATUS PROGRAMMABLE A/B PRESCALER COUNTERS N DELAY N DIVIDER DIVIDE DIVIDE DIVIDE DIVIDE Figure 26. Detailed Block Diagram Rev Page AD9518-1 CPRSET VCP LD LOCK DETECT HOLD PHASE CHARGE FREQUENCY CP PUMP DETECTOR STATUS OUT0 OUT0 LVPECL OUT1 OUT1 OUT2 OUT2 LVPECL OUT3 ...
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... AD9518-1 THEORY OF OPERATION OPERATIONAL CONFIGURATIONS The AD9518 can be configured in several ways. These configurations must be set up by loading the control registers (see Table 41 and Table 42 through Table 48). Each section or function must be individually programmed by setting the appropriate bits in the corresponding control register or registers. ...
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... REFMON DISTRIBUTION REFERENCE R PROGRAMMABLE DIVIDER R DELAY VCO STATUS A/B PROGRAMMABLE COUNTERS N DELAY N DIVIDER DIVIDE BY 0 DIVIDE DIVIDE DIVIDE Rev Page AD9518-1 CPRSET VCP LD LOCK DETECT HOLD PHASE CHARGE FREQUENCY CP PUMP DETECTOR STATUS OUT0 OUT0 LVPECL OUT1 OUT1 OUT2 OUT2 LVPECL OUT3 ...
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... LOW DROPOUT BYPASS REGULATOR (LDO) LF VCO CLK CLK PD DIGITAL SYNC LOGIC RESET SCLK SERIAL SDIO CONTROL SDO PORT CS AD9518-1 Table 23. Settings When Using Internal VCO Register 0x10<1:0> = 00b 0x10 to 0x1E 0x18<0> 0x232<0> 0x18<0> 0x232<0> 0x1E0<2:0> 0x1E1<0> 0x1E1<1> GND RSET REFMON DISTRIBUTION REFERENCE R ...
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... PLL. Make sure to select the proper PFD polarity for the VCO/VCXO being used. Table 26. Setting the PFD Polarity Register Function 0x10<7> PFD polarity positive (higher control voltage produces higher frequency) 0x10<7> PFD polarity negative (higher control voltage produces lower frequency) Rev Page AD9518-1 ...
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... STATUS REFIN (REF1) REFIN (REF2) LOW DROPOUT BYPASS REGULATOR (LDO) LF VCO CLK CLK PD DIGITAL SYNC LOGIC RESET SCLK SERIAL SDIO CONTROL SDO PORT CS AD9518-1 VS GND RSET REFMON DISTRIBUTION REFERENCE R PROGRAMMABLE DIVIDER R DELAY VCO STATUS A/B PROGRAMMABLE PRESCALER COUNTERS N DELAY N DIVIDER DIVIDE ...
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... ADIsimCLK™ (V1.2 or later free program that can help with the design and exploration of the capabilities and features of the AD9518, including the design of the PLL loop filter available at www.analog.com/clocks. Phase Frequency Detector (PFD) The PFD takes inputs from the R counter and N counter and produces an output proportional to the phase and frequency difference between them ...
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... PLL Reference Inputs The AD9518 features a flexible PLL reference input circuit that allows either a fully differential input or two separate single- ended inputs. The input frequency range for the reference inputs is specified in Table 2. Both the differential and the single-ended inputs are self-biased, allowing for easy ac coupling of input signals ...
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... The prescaler modes of operation are given in Table 43, 0x16<2:0>. Not all modes are available at all frequencies (see Table 2). When operating the AD9518 in dual modulus mode (P//P + 1), the equation used to relate input reference frequency to VCO output frequency is ...
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... use the dual modulus mode 4/5 with and B Counters The AD9518 B counter can be bypassed (B = 1). This B counter bypass mode is only valid when using the prescaler in FD mode. When the divide is a fixed divide 16, or 32. Unlike the R counter actually a zero. The B counter must be ≥ ...
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... The number of consecutive PFD cycles required for lock is programmable (0x18<6:5>). Analog Lock Detect (ALD) The AD9518 provides an ALD function that may be selected for use at the LD pin. There are two versions of ALD: • N-channel open-drain lock detect. This signal requires a pull-up resistor to the positive supply, VS ...
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... AD9518-1 Holdover The AD9518 PLL has a holdover function. Holdover is implemented by putting the charge pump into a high impedance state. This is useful when the PLL reference clock is lost. Holdover mode allows the VCO to maintain a relatively constant frequency even though there is no reference clock. ...
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... Frequency Status Monitors The AD9518 contains three frequency status monitors that are used to indicate if the PLL reference (or references in the case of single-ended mode) and the VCO have fallen below a threshold frequency ...
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... REFIN clock. The calibration requires that the PLL be set up properly to lock the PLL loop and that the REFIN clock be present. During the first initialization after a power- reset of the AD9518, a VCO calibration sequence is initiated by setting 0x18<0> = 1b. This can be done as part of the initial setup before executing update registers (0x232<0> = 1b). ...
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... The divider outputs can also be set to start high or start low. Internal VCO or External CLK as Clock Source The clock distribution of the AD9518 has two clock input sources: internal VCO and an external clock connected to the CLK/ CLK pins. Either the internal VCO or CLK must be chosen as the source of the clock signal to distribute ...
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... AD9518-1 Clock Frequency Division The total frequency division is a combination of the VCO divider (when used) and the channel divider. When the VCO divider is used, the total division from the VCO or CLK to the output is the product of the VCO divider ( and the division of the channel divider. Table 31 indicates how the frequency division for a channel is set ...
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... DIVIDER 0 DIVIDER 1 DIVIDER 2 Synchronizing the Outputs—SYNC Function The AD9518 clock outputs can be synchronized to each other. Outputs can be individually excluded from synchronization. Synchronization consists of setting the nonexcluded outputs to a preset set of static conditions and subsequently releasing these outputs to continue clocking at the same instant with the preset conditions applied ...
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... SYNC signal with respect to the clock edges inside the AD9518. The delay from the SYNC rising edge to the beginning of synchronized output clocking is between 14 and 15 cycles of clock at the channel divider input, plus either one cycle of the VCO ...
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... If the pins are not connected (unused acceptable to use the total power-down mode. RESET MODES The AD9518 has several ways to force the chip into a reset condition that restores all registers to their default values and makes these settings active. can be S_LVPECL Power-On Reset— ...
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... LVPECL output circuitry from damage that could be caused by certain termination and load configurations when tristated. Because this is not a complete power-down, it can be called sleep mode. When the AD9518 power-down, the chip is in the following state: • The PLL is off (asynchronous power-down). • The VCO is off. ...
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... SDIO 16 Figure 42. Serial Control Port GENERAL OPERATION OF SERIAL CONTROL PORT A write or a read operation to the AD9518 is initiated by pulling CS low. CS stalled high is supported in modes where three or fewer bytes of data (plus instruction data) are transferred (see Table 37). In these modes, CS can temporarily return high on any byte boundary, allowing time for the system controller to process the next byte ...
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... Only Bits A9:A0 are needed to cover the range of the 0x232 registers used by the AD9518. Bits A12:A10 must always be 0b. For multibyte transfers, this address is the starting byte address. In MSB first mode, subsequent bytes decrement the address ...
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... Figure 47. Timing Diagram for Serial Control Port Register Read A9 A10 A11 A12 REGISTER (N) DATA Rev Page REGISTER (N – 1) DATA REGISTER (N – 2) DATA REGISTER (N – 3) DATA t C DON'T CARE DON'T CARE REGISTER ( DATA AD9518-1 LSB I0 A0 DON'T CARE DON'T CARE DON'T CARE DON'T CARE DON'T CARE DON'T CARE ...
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... AD9518 SCLK SDIO Table 40. Serial Control Port Timing Parameter Description t Setup time between data and rising edge of SCLK DS t Hold time between data and rising edge of SCLK DH t Period of the clock CLK t Setup time between CS falling edge and SCLK rising edge (start of communication cycle) ...
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... Comparator Disable Enable Reserved Holdover REF2 VCO Active Selected Frequency > Threshold Blank Reserved Blank Rev Page AD9518-1 Bit 2 Bit 1 Bit 0 (LSB) Soft Reset LSB First SDO Active Readback Active Registers PLL Power-Down Prescaler P Antibacklash Pulse Width VCO Calibration Divider VCO Cal ...
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... AD9518-1 Addr Bit 7 (Hex) Parameter (MSB) Bit 6 LVPECL Outputs F0 OUT0 F1 OUT1 F2 OUT2 F3 OUT3 F4 OUT4 F5 OUT5 F6 to 13F 140 to 143 144 to 18F LVPECL Channel Dividers 190 Divider 0 Divider 0 Low Cycles (PECL) 191 Divider 0 Divider 0 Bypass Nosync 192 Blank 193 Divider 1 Divider 1 Low Cycles ...
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... System 230 Power-Down and SYNC 231 Update All Registers 232 Update All Registers Bit 5 Bit 4 Bit 3 Reserved Blank Blank Rev Page AD9518-1 Bit 2 Bit 1 Bit 0 (LSB) Power- Power- Soft SYNC Down Down SYNC Distribution Reference Reserved Update All Registers (Self- Clearing ...
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... AD9518-1 REGISTER MAP DESCRIPTIONS Table 42 through Table 48 provide a detailed description of each of the control register functions. The registers are listed by hexadecimal address. Reference to a specific bit or range of bits within a register is indicated by angle brackets. For example, <3> refers to Bit 3, and <5:2> refers to the range of bits from Bit 5 through Bit 2. ...
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... CP 0.6 1.2 1.8 2.4 3.0 3.6 4.2 4.8 Charge Pump Mode High impedance state. Force source current (pump up). Force sink current (pump down). Normal operation. Mode Normal operation. Asynchronous power-down. Normal operation. Synchronous power-down. supply voltage. CP /2. CP Rev Page AD9518-1 ...
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... AD9518-1 Reg. Addr (Hex) Bit(s) Name Description 16 <5> Reset A and B Resets A and B counters (part of N divider). Counters <5> normal. <5> resets A and B counters. 16 <4> Reset All Resets R, A, and B counters. Counters <4> normal. <4> resets R, A, and B counters. 16 <3> B Counter B counter bypass. This is valid only when operating the prescaler in FD mode. ...
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... REF1 frequency) AND (status of REF2 frequency). (DLD) AND (status of selected reference) AND (status of VCO). Status of VCO frequency (active low). Selected reference (low = REF2, high = REF1). Digital lock detect (DLD); active low. Holdover active (active low). LD pin comparator output (active low). AD9518-1 ...
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... AD9518-1 Reg. Addr (Hex) Bit(s) Name Description 18 <0> VCO Cal Bit used to initiate the VCO calibration. This bit must be toggled from the active registers. The sequence Now to initiate a calibration is: program to 0, followed by an update bit (0x232<0>); then program to 1, followed by another update bit (0x232<0>). This sequence gives complete control over when the VCO calibration occurs relative to the programming of other registers that can impact the calibration ...
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... Selected reference (low = REF1, high = REF2 LVL Digital lock detect (DLD); active low LVL Holdover active (active high LVL LD pin comparator output (active high LVL VS (PLL supply DYN REF1 clock (differential reference when in differential mode DYN REF2 clock (not available in differential mode). Rev Page AD9518-1 ...
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... AD9518-1 Reg. Addr (Hex) Bit(s) Name Description <4> <3> <2> <1> <7> Disable Disables or enables the switchover deglitch circuit. Switchover <7> enables switchover deglitch circuit. Deglitch <7> disables switchover deglitch circuit. 1C <6> Select REF2 If 0x1C<5> selects reference for PLL. <6> selects REF1. ...
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... Readback register; indicates if the frequency of the signal at REF2 is greater than the threshold frequency Frequency > set by 0x1A<6>. Threshold <1> REF1 frequency is less than threshold frequency. <1> REF1 frequency is greater than threshold frequency. 1F <0> Digital Lock Readback register; digital lock detect. Detect <0> PLL is not locked. <0> PLL is locked. Rev Page AD9518-1 ...
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... AD9518-1 Table 44. LVPECL Outputs Reg. Addr (Hex) Bit(s) Name Description F0 <4> OUT0 Invert Sets the output polarity. <4> noninverting. <4> inverting. F0 <3:2> OUT0 LVPECL Sets the LVPECL output differential voltage (V Differential <3> <2> V Voltage <1:0> OUT0 LVPECL power-down modes. Power-Down <1> ...
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... Normal operation. Partial power-down, reference on; use only if there are no external load resistors. Partial power-down, reference on, safe LVPECL power-down. Total power-down, reference off; use only if there are no external load resistors. Rev Page AD9518-1 Output On Off Off Off Output On Off ...
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... AD9518-1 Table 45. LVPECL Channel Dividers Reg. Addr (Hex) Bit(s) Name 190 <7:4> Divider 0 Low Cycles 190 <3:0> Divider 0 High Cycles 191 <7> Divider 0 Bypass 191 <6> Divider 0 Nosync 191 <5> Divider 0 Force High 191 <4> Divider 0 Start High 191 <3:0> Divider 0 Phase Offset 192 < ...
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... Description <2> <1> <0> <4> normal operation. <4> power-down. <3> normal operation. <3> power-down. Power down both VCO and CLK input. <2> normal operation. <2> power-down. Rev Page AD9518-1 Divide Output static Output static Output static ...
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... AD9518-1 Reg. Addr (Hex) Bit(s) Name 1E1 <1> Select VCO or CLK 1E1 <0> Bypass VCO Divider Table 47. System Reg. Addr (Hex) Bit(s) Name 230 <2> Power-Down SYNC 230 <1> Power-Down Distribution Reference 230 <0> Soft SYNC Table 48. Update All Registers Reg. ...
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... LVPECL CLOCK DISTRIBUTION The LVPECL outputs of the AD9518 provide the lowest jitter clock signals available from the AD9518. The LVPECL outputs (because they are open-emitter) require a dc termination to bias the output transistors. The simplified equivalent circuit in Figure 41 shows the LVPECL output stage ...
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... PIN 1 INDICATOR 1.00 12° MAX 0.85 0.80 SEATING PLANE ORDERING GUIDE Model Temperature Range 1 AD9518-1BCPZ −40°C to +85°C 1 AD9518-1BCPZ-REEL7 −40°C to +85°C 1 AD9518-1/PCBZ RoHS Compliant Part. 7.00 BSC SQ 0.60 MAX 37 36 TOP 6.75 VIEW BSC SQ 0.50 0. 0.30 0.80 MAX ...
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... NOTES Rev Page AD9518-1 ...
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... AD9518-1 NOTES ©2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06430-0-9/07(0) Rev Page ...