AD9850/FSPCB Analog Devices Inc, AD9850/FSPCB Datasheet - Page 11

D/A Converter (D-A) IC

AD9850/FSPCB

Manufacturer Part Number
AD9850/FSPCB
Description
D/A Converter (D-A) IC
Manufacturer
Analog Devices Inc
Datasheet

Specifications of AD9850/FSPCB

No. Of Bits
32 Bit
Mounting Type
Surface Mount
Interface Type
Serial, Parallel
Package / Case
28-SSOP
Rohs Status
RoHS non-compliant
Main Purpose
Timing, Direct Digital Synthesis (DDS)
Utilized Ic / Part
AD9850/FS
Secondary Attributes
-
Embedded
-
Primary Attributes
-
Lead Free Status / Rohs Status
Not Compliant
REV. H
COS OUT
DAC STROBE
RESET
Figure 8. Parallel Load Power-Down Sequence/Internal Operation
CLKIN
DATA (W0)
DATA (W0)
Figure 9. Parallel Load Power-Up Sequence/Internal Operation
W CLK
W CLK
FQ UD
FQ UD
CLKIN
CLKIN
NOTE: THE TIMING DIAGRAM ABOVE SHOWS THE MINIMAL AMOUNT OF RESET TIME
NEEDED BEFORE WRITING TO THE DEVICE. HOWEVER, THE MASTER RESET DOES NOT
HAVE TO BE SYNCHRONOUS WITH THE CLKIN IF THE MINIMAL TIME IS NOT REQUIRED.
RESULTS OF RESET:
SYMBOL
t
t
t
t
t
RH
RL
RR
RS
OL
Figure 7. Master Reset Timing Sequence
– FREQUENCY/PHASE REGISTER SET TO 0
– ADDRESS POINTER RESET TO W0
– POWER-DOWN BIT RESET TO 0
– DATA INPUT REGISTER UNEFFECTED
t
RH
DEFINITION
CLK DELAY AFTER RESET RISING EDGE
RESET FALLING EDGE AFTER CLK
RECOVERY FROM RESET
MINIMUM RESET WIDTH
RESET OUTPUT LATENCY
INTERNAL CLOCKS ENABLED
t
RS
XXXXX000
XXXXX100
–11–
t
OL
t
RL
INTERNAL CLOCKS DISABLED
t
RR
MINIMUM
3.5ns
3.5ns
2 CLK CYCLES
5 CLK CYCLES
13 CLK CYCLES
COS (0)
AD9850

Related parts for AD9850/FSPCB