ADM8691ARN Analog Devices Inc, ADM8691ARN Datasheet - Page 12

• Manufacturer Part Number: ADM8691ARN
• Description: IMPROVED ADM691 I.C.
• Manufacturer: Analog Devices Inc
• Type: Battery Backup Circuitr

Specifications of ADM8691ARN

• Rohs Compliant: NO
• Rohs Status: RoHS non-compliant
• Number Of Voltages Monitored: 1
• Output: Push-Pull, Push-Pull
• Reset: Active High/Active Low
• Reset Timeout: 35 ms Minimum
• Voltage - Threshold: 4.65V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-SOIC (3.9mm Width)

ADM8690/ADM8691/ADM8692/ADM8693/ADM8694/ADM8695
On the ADM8690/ADM8692 the watchdog timeout period is
fixed at 1.6 seconds and the reset pulse width is fixed at 50 ms.
On the ADM8694 the watchdog timeout period is also 1.6 seconds
but the reset pulse width is fixed at 200 ms. The ADM8691/
ADM8693/ADM8695 allow these times to be adjusted, as shown
in Table 5. Figure 17, Figure 18, Figure 19, and Figure 20 show
the various oscillator configurations that can be used to adjust
the reset pulse width and watchdog timeout period.
The internal oscillator is enabled when OSC SEL is high or
floating. In this mode, OSC IN selects between the 1.6 second
and 100 ms watchdog timeout periods. With OSC IN connected
high or floating, the 1.6 second timeout period is selected; and
with it connected low, the 100 ms timeout period is selected. In
either case, the timeout period is 1.6 seconds immediately after
a reset. This gives the microprocessor time to reinitialize the
system. If OSC IN is low, the 100 ms watchdog period becomes
effective after the first transition of WDI. The software should
be written such that the input/output port driving WDI is left in
its power-up reset state until the initialization routines are
completed and the microprocessor is able to toggle WDI at the
minimum watchdog timeout period of 70 ms.
WATCHDOG OUTPUT (WDO)
The Watchdog Output WDO (ADM8691/ADM8693/ADM8695)
provides a status output that goes low if the watchdog timer
times out and remains low until set high by the next transition
on the watchdog input. WDO is also set high when V
below the reset threshold.
Figure 19. Internal Oscillator (1.6 Second Watchdog)
0 TO 500kHz
CLOCK
C
OSC
NC
NC
Figure 17. External Clock Source
Figure 18. External Capacitor
8
7
8
7
OSC SEL
OSC IN
8
7
OSC SEL
OSC IN
ADM8691/
ADM8693/
ADM8695
OSC SEL
OSC IN
ADM8691/
ADM8693/
ADM8695
ADM8691/
ADM8693/
ADM8695
CC
goes
Rev. A | Page 12 of 20
CE GATING AND RAM WRITE PROTECTION
(ADM8691/ADM8693/ADM8695)
The ADM8691/ADM8693/ADM8695 products include
memory protection circuitry that ensures the integrity of data
in memory by preventing write operations when V
invalid level. There are two additional pins ( CE
that can be used to control the chip enable or write inputs of
CMOS RAM. When V
of CE
reset voltage threshold or V
high, independent of CE
CE
backed up CMOS RAM. This ensures the integrity of the data in
memory by preventing write operations when V
invalid level. Similar protection of EEPROMs can be achieved
using the CE
LOW LINE
RESET
CE
OUT
CE
V
OUT
IN
CC
IN
typically drives the CE , CS , or write input of battery
, with a 3 ns propagation delay. When V
Figure 20. Internal Oscillator (100 ms Watchdog)
OUT
CE
V2
IN
to drive the store or write inputs.
NC
t
t 1 = RESET TIME
V1 = RESET VOLTAGE THRESHOLD LOW
V2 = RESET VOLTAGE THRESHOLD HIGH
HYSTERESIS = V2–V1
1
Figure 22. Chip Enable Timing
Figure 21. Chip Enable Gating
ADM8691
ADM8693
ADM8695
CC
V
V
CC
CC
IN
8
7
is present, CE
.
LOW = 0
OK = 1
V1
BATT
OSC SEL
OSC IN
, an internal gate forces CE
ADM8691/
ADM8693/
ADM8695
V2
OUT
t
1
is a buffered replica
CE
OUT
IN
CC
CC
and CE
falls below the
CC
is at an
is at an
OUT
OUT
)
V1