AM29LV160DT-90EI Spansion Inc., AM29LV160DT-90EI Datasheet - Page 23

• Manufacturer Part Number: AM29LV160DT-90EI
• Description: IC,EEPROM,NOR FLASH,1MX16/2MX8,CMOS,TSSOP,48PIN,PLASTIC
• Manufacturer: Spansion Inc.

Specifications of AM29LV160DT-90EI

• Rohs Compliant: NO

Any commands written to the device during the Em-
bedded Program Algorithm are ignored. Note that a
hardware reset immediately terminates the program-
m i n g o p e ra t i o n . T h e B y t e P r o gra m c o m m a n d
sequence should be reinitiated once the device has
reset to reading array data, to ensure data integrity.
Programming is allowed in any sequence and across
sector boundaries. A bit cannot be programmed
from a “0” back to a “1”. Attempting to do so may
halt the operation and set DQ5 to “1,” or cause the
Data# Polling algorithm to indicate the operation was
successful. However, a succeeding read will show that
the data is still “0”. Only erase operations can convert
a “0” to a “1”.
Unlock Bypass Command Sequence
The unlock bypass feature allows the system to pro-
gram bytes or words to the device faster than using the
standard program command sequence. The unlock
bypass command sequence is initiated by first writing
two unlock cycles. This is followed by a third write
cycle containing the unlock bypass command, 20h.
The device then enters the unlock bypass mode. A
two-cycle unlock bypass program command sequence
is all that is required to program in this mode. The first
cycle in this sequence contains the unlock bypass pro-
gram command, A0h; the second cycle contains the
program address and data. Additional data is pro-
grammed in the same manner. This mode dispenses
with the initial two unlock cycles required in the stan-
dard program command sequence, resulting in faster
total programming time. Table 9 shows the require-
ments for the command sequence.
During the unlock bypass mode, only the Unlock By-
pass Program and Unlock Bypass Reset commands
are valid. To exit the unlock bypass mode, the system
must issue the two-cycle unlock bypass reset com-
mand sequence. The first cycle must contain the data
Note: See Table 9 for program command sequence.
Chip Erase Command Sequence
Chip erase is a six bus cycle operation. The chip erase
command sequence is initiated by writing two unlock
cycles, followed by a set-up command. Two additional
unlock write cycles are then followed by the chip erase
command, which in turn invokes the Embedded Erase
algorithm. The device does not require the system to
preprogram prior to erase. The Embedded Erase algo-
rithm automatically preprograms and verifies the entire
memory for an all zero data pattern prior to electrical
erase. The system is not required to provide any con-
trols or timings during these operations. Table 9 shows
22358B7 May 5, 2006
Figure 3. Program Operation
D A T A
Am29LV160D
S H E E T
90h; the second cycle the data 00h. Addresses are
don’t care for both cycles. The device then returns to
reading array data.
Figure 3 illustrates the algorithm for the program oper-
ation. See the Erase/Program Operations table in “AC
Characteristics” for parameters, and to Figure 17 for
timing diagrams.
the address and data requirements for the chip erase
command sequence.
Any commands written to the chip during the Embed-
ded Erase algor ithm are ignored . Note that a
hardware reset during the chip erase operation im-
mediately terminates the operation. The Chip Erase
command sequence should be reinitiated once the de-
vice has returned to reading array data, to ensure data
integrity.
The system can determine the status of the erase op-
eration by using DQ7, DQ6, DQ2, or RY/BY#. See
“Write Operation Status” for information on these sta-
tus bits. When the Embedded Erase algorithm is
complete, the device returns to reading array data and
addresses are no longer latched.
Increment Address
in progress
Embedded
algorithm
Program
No
Command Sequence
Write Program
Last Address?
Programming
from System
Verify Data?
Completed
Data Poll
START
Yes
Yes
No
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