CS43L21-CNZR Cirrus Logic Inc, CS43L21-CNZR Datasheet - Page 32

• Manufacturer Part Number: CS43L21-CNZR
• Description: IC 98dB 96kHz Low Power Stereo DAC
• Manufacturer: Cirrus Logic Inc

Specifications of CS43L21-CNZR

• Number Of Bits: 24
• Data Interface: Serial
• Number Of Converters: 2
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -10°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 32-QFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1282 - BOARD EVAL FOR CS43L21 DAC
• Power Dissipation (max): -
• Settling Time: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

32
4.8
1. Audible pops.
Power Off Transition
Recommended Power-Down Sequence
To minimize audible pops when turning off or placing the D/A in standby,
1. Mute the DAC’s.
2. Set the PDN bit in the power control register to ‘1’b. The D/A will not power down until it reaches a fully
3. Bring RESET low.
muted sate. Do not remove MCLK until after the part has fully muted. Note that it may be necessary to
disable the soft ramp and/or zero cross volume transitions to achieve faster muting/power down.
1. Pops suppressed.
Reset Transition
ERROR: Power removed
Hardware Mode
Minimal feature
set support.
1. No audio signal generated.
2. Control Port Registers reset
to default.
No
Off Mode (Power Applied)
1. No audio signal
generated.
Control Port Valid
Write Seq. within
RESET = Low?
Control Port
No Power
10 ms?
Active
No
ERROR: MCLK/LRCK ratio change
Registers setup to
Figure 17. Initialization Flow Chart
desired settings.
Software Mode
Yes
Yes
RESET = Low
Audio signal generated per control port or stand-
1. Aout bias = last audio sample.
2. DAC Modulators stop operation.
3. Audible pops.
No
ERROR: MCLK removed
Analog Output Freeze
1. LRCK valid.
2. SCLK valid.
3. Audio samples
processed.
Sub-Clocks Applied
Normal Operation
1. VQ Charged to
quiescent voltage.
2. Filtx+ Charged.
MCLK Applied?
PDN bit = '1'b?
Digital/Analog
Output Muted
alone settings.
Charge Caps
MCLK/LRCK
20 ms delay
Ratio?
Valid
Valid
Yes
No
Yes
No
Headphone Amp
Charge Pump
PDN bit set to '1'b
(software mode only)
Initialization
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50 ms delay
20
µ
s delay
1. No audio signal generated.
2. Control Port Registers retain
settings.
1. Pops suppressed.
Headphone Amp
Powered Down
Standby Mode
20
Transition
Stand-By
CS43L21
µ
s delay
DS723A1