CS5344-CZZR Cirrus Logic Inc, CS5344-CZZR Datasheet - Page 14

• Manufacturer Part Number: CS5344-CZZR
• Description: IC,A/D CONVERTER,DUAL,24-BIT,TSSOP,10PIN
• Manufacturer: Cirrus Logic Inc

14
4.1.2
4.1.3
4.1.2.1
Master Mode Operation
As clock Master, the CS5343/4 generates LRCK and SCLK synchronously on-chip.
available sample rates and associated clock ratios in Master Mode.
During power-up in Master Mode, the LRCK and SCLK pins are inputs to configure speed mode and the
output clock ratio. The LRCK pin is pulled low internally to select Single-Speed Mode by default, but Dou-
ble-Speed Mode is accessed with a 10 kΩ pull-up resistor from LRCK to VA as shown in
larly, the SCLK pin is internally pulled-low by default to select a 256x MCLK/LRCK ratio, but a
MCLK/LRCK ratio of 348x is accessed with a 10 kΩ pull-up resistor from SCLK to VA as shown in
Following the power-up routine, the LRCK and SCLK pins become clock outputs.
Master Clock
The CS5343/4 requires a Master clock (MCLK) which runs the internal sampling circuits and digital filters.
There is also an internal MCLK divider which is automatically activated based on the frequency of the
MCLK.
LRCK
SCLK
Pin
Double-Speed Mode
Sample Rate (kHz)
Sample Rate (kHz)
Single-Speed Mode
Table 4
Speed Mode
Master Mode Speed Selection
44.1
88.2
32
48
96
Table 3. Speed Modes and the Associated Sample Rates (Fs) in Master Mode
lists some common audio output sample rates and the required MCLK frequency.
Table 5. Common MCLK Frequencies in Master and Slave Modes
Internal Pull-Down to GND (100 kΩ)
Internal Pull-Down to GND (100 kΩ)
External Pull-Up to VA (10 kΩ)
External Pull-Up to VA (10 kΩ)
Table 4. Speed Mode Selection in Master Mode
Resistor Option
MCLK/LRCK
Speed Mode
Speed Mode
Ratio
256x
512x
384x
768x
128x
256x
192x
384x
DSM
SSM
SSM
SSM
DSM
Master and Slave Mode
SCLK/LRCK
11.289
12.288
11.289
12.288
Ratio
8.912
256x
128x
64
64
64
64
64
64
64
64
MCLK(MHz)
MCLK(MHz)
16.384
22.579
24.576
24.576
22.579
512x
256x
Input Sample Rate Range (kHz)
Single-Speed Mode (default)
256x MCLK/LRCK (default)
Clock Configuration
Double-Speed Mode
384x MCLK/LRCK
12.288
16.934
18.432
16.934
18.432
86 - 108
86 - 108
86 - 108
86 - 108
384x
192x
4 - 54
4 - 54
4 - 54
4 - 54
MCLK (MHz)
MCLK (MHz)
Table 3
CS5343/4
Table
shows the
24.576
33.868
36.864
33.868
36.864
DS687A4
768x
384x
Table
4. Simi-
4.