CS8406-CZZR Cirrus Logic Inc, CS8406-CZZR Datasheet - Page 17

• Manufacturer Part Number: CS8406-CZZR
• Description: IC,Digital Audio Transmitter,CMOS,TSSOP,28PIN,PLASTIC
• Manufacturer: Cirrus Logic Inc
• Type: Digital Audio Interface Transmitterr

Specifications of CS8406-CZZR

• Applications: Automotive Audio
• Mounting Type: Surface Mount
• Package / Case: 28-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1017 - BOARD EVAL FOR CS8416 RCVR
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: Q4266681

DS580F4
6.2
SDA
SCL
SDA
SCL
START
START
I²C Mode
In I²C Mode, SDA is a bidirectional data line. Data is clocked into and out of the part by the clock, SCL. There
is no CS pin. Pins AD0, AD1, and AD2 form the three least significant bits of the chip address and should
be connected to VL or GND as desired.
The signal timing for both a read and write cycle are shown in
defined as a falling transition of SDA while the clock is high. A Stop condition is a rising transition while the
clock is high. All other transitions of SDA occur while the clock is low. The first byte sent to the CS8406 after
a Start condition consists of a 7 bit chip address field and a R/W bit (high for a read, low for a write). The
upper 4 bits of the 7-bit address field are fixed at 0010. To communicate with a CS8406, the chip address
field, which is the first byte sent to the CS8406, should match 0010 followed by the settings of the AD2, AD1,
and AD0 pins. The eighth bit of the address is the R/W bit. If the operation is a write, the next byte is the
Memory Address Pointer (MAP) which selects the register to be read or written. If the operation is a read,
the contents of the register pointed to by the MAP will be output. The MAP automatically increments, so
consecutive registers can read from or written to easily. Each byte is separated by an acknowledge bit
(ACK). The ACK bit is output from the CS8406 after each input byte is read, and is input to the CS8406 from
the microcontroller after each transmitted byte.
Since the read operation cannot set the MAP, an aborted write operation is used as a preamble. As shown
in
Figure
0 0 1 0 AD2 AD1 AD0 0
0
0
0
CHIP ADDRESS (WRITE)
CHIP ADDRESS (WRITE)
1
0
1
2
1
12, the write operation is aborted after the acknowledge for the MAP by sending a stop condition.
2
3
0 AD2 AD1 AD0 0
3
4
4
5
6
5
7
6
ACK
Figure 11. Control Port Timing, I²C Slave Mode Write
Figure 12. Control Port Timing, I²C Slave Mode Read
8
7
9
ACK
8
10 11
6
9
5
12 13 14 15
10 11
4
MAP
6
3
5
2
12
MAP
4
1
13 14 15
0
16
3
ACK
STOP
17 18
2
START
1
16 17 18
19
ACK
0 0 1 0 AD2 AD1 AD0 1
20 21 22 23 24
CHIP ADDRESS (READ)
7
19
6
DATA
Figure 11
24 25
1
0
25
ACK
26 27 28
26
ACK
and
27 28
7
7
DATA
DATA +1
6
Figure
0
ACK
1
DATA +1
12. A Start condition is
0
7
0
7
DATA +n
6
DATA + n
7
1
CS8406
0
0
ACK
NO
ACK
STOP
STOP
17