CY7C1021BNL-15VXCT Cypress Semiconductor Corp, CY7C1021BNL-15VXCT Datasheet

CY7C1021BNL-15VXCT

CY7C1021BNL-15VXCT

Manufacturer Part Number
CY7C1021BNL-15VXCT
Description
CY7C1021BNL-15VXCT
Manufacturer
Cypress Semiconductor Corp
Datasheet

Specifications of CY7C1021BNL-15VXCT

Format - Memory
RAM
Memory Type
SRAM - Asynchronous
Memory Size
1M (64K x 16)
Speed
15ns
Interface
Parallel
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
0°C ~ 70°C
Package / Case
44-SOJ
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
Cypress Semiconductor Corporation
Document #: 001-06494 Rev. *C
Note
Logic Block Diagram
1. For best practice recommendations, refer to the Cypress application note,
Temperature ranges
High speed
Complementary metal oxide semiconductor (CMOS) for
optimum speed/power
Low active power
Automatic power down when deselected
Independent control of upper and lower bits
Available in Pb-free and non Pb-free 44-pin TSOP II and
44-pin 400-mil-wide SOJ
Commercial: 0 °C to 70 °C
Industrial: –40 °C to 85 °C
Automotive-A: –40 °C to 85 °C
Automotive-E: –40 °C to 125 °C
t
t
825 mW (maximum)
AA
AA
= 10 ns (Commercial)
= 15 ns (Automotive)
A
A
A
A
A
A
A
A
4
3
2
1
0
7
6
5
Data In Drivers
Column Decoder
512 X 2048
RAM Array
64K x 16
198 Champion Court
SRAM System Design
Functional Description
The CY7C1021BN/CY7C10211BN
CMOS static RAM organized as 65,536 words by 16 bits. This
device has an automatic power down feature that significantly
reduces power consumption when deselected.
Writing to the device is accomplished by taking Chip Enable (CE)
and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is
LOW, then data from the input/output (I/O) pins (I/O
I/O
through A
I/O pins (I/O
on the address pins (A
Reading from the device is accomplished by taking CE and
Output Enable (OE) LOW while forcing WE HIGH. If BLE is LOW,
then data from the memory location specified by the address pins
appears on I/O
appears on I/O
complete description of read and write modes.
The I/O pins (I/O
state when the device is deselected (CE HIGH), the outputs are
disabled (OE HIGH), the BHE and BLE are disabled (BHE, BLE
HIGH), or during a write operation (CE LOW, WE LOW).
The CY7C1021BN/CY7C10211BN is available in standard
44-pin TSOP type II and 44-pin 400-mil-wide SOJ packages.
Use part number CY7C10211BN when ordering parts with 10 ns
t
AA
8
and CY7C1021BN when ordering 12 ns and 15 ns t
), is written into the location specified on the address pins (A
15
1 Mbit (64K x 16) Static RAM
San Jose
). If Byte High Enable (BHE) is LOW, then data from
Guidelines-AN1064.
9
through I/O
CY7C1021BN, CY7C10211BN
1
9
to I/O
1
to I/O
I/O
I/O
through I/O
WE
OE
BHE
CE
BLE
1
9
–I/O
–I/O
,
8
0
. If BHE is LOW, then data from memory
CA 95134-1709
16
through A
. See the
8
16
16
) is written into the location specified
16
) are placed in a high impedance
15
Truth Table on page 9
[1]
Revised June 11, 2010
).
is a high performance
• 408-943-2600
1
AA
through
.
for a
0
[+] Feedback

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CY7C1021BNL-15VXCT Summary of contents

Page 1

... Note 1. For best practice recommendations, refer to the Cypress application note, Cypress Semiconductor Corporation Document #: 001-06494 Rev. *C CY7C1021BN, CY7C10211BN 1 Mbit (64K x 16) Static RAM Functional Description The CY7C1021BN/CY7C10211BN CMOS static RAM organized as 65,536 words by 16 bits. This device has an automatic power down feature that significantly reduces power consumption when deselected ...

Page 2

Contents Features ................................................................................1 Functional Description ........................................................1 Logic Block Diagram ...........................................................1 Contents ...............................................................................2 Selection Guide ...................................................................3 Pin Configuration ................................................................3 Pin Definitions ................................................................3 Maximum Ratings ................................................................4 Operating Range ..................................................................4 Electrical Characteristics ....................................................4 Capacitance .........................................................................5 Thermal Resistance .............................................................5 Document #: 001-06494 Rev. *C ...

Page 3

Selection Guide Description Maximum access time (ns) Maximum operating current (mA) Maximum CMOS standby current (mA) Commercial/Industrial Pin Configuration Pin Definitions Pin Name Pin Number A –A 1–5,18–21, 24–27, 42– I/O –I/O 7–10, 13–16, 29–32 35–38 ...

Page 4

Maximum Ratings Exceeding the maximum ratings may impair the useful life of the device. These user guidelines are not tested. Storage temperature ................................ –65 °C to +150 °C Ambient temperature with power applied ........................................... –55 °C to +125 °C [2] ...

Page 5

Capacitance [4] Parameter Description C Input capacitance IN C Output capacitance OUT Thermal Resistance [4] Parameter Description Θ Thermal resistance JA (junction to ambient) Θ Thermal resistance JC (junction to case) R 481Ω OUTPUT OUTPUT OUTPUT OUTPUT R2 ...

Page 6

Switching Characteristics [5] Over the operating range Parameter Description Read Cycle t Read cycle time RC t Address to data valid AA t Data hold from address change OHA t CE LOW to data valid ACE t OE LOW to ...

Page 7

Switching Waveforms ADDRESS DATA OUT PREVIOUS DATA VALID Figure 4. Read Cycle No. 2 (OE Controlled) ADDRESS CE t ACE OE t DOE BHE, BLE t LZOE t DBE t LZBE HIGH IMPEDANCE DATA OUT t LZCE ...

Page 8

Figure 5. Write Cycle No. 1 (CE Controlled) ADDRESS ADDRESS BHE, BLE DATA I/O Figure 6. Write Cycle No. 2 (BLE or BHE Controlled) ADDRESS t SA BHE, BLE WE CE DATA I/O Notes 12. Data ...

Page 9

Figure 7. Write Cycle No. 3 (WE Controlled, OE LOW) ADDRESS BHE, BLE DATA I/O Truth Table BLE BHE I High Data ...

Page 10

... Cypress maintains a worldwide network of offices, solution centers, manufacturers’ representatives and distributors. To find the office closest to you, visit us at http://www.cypress.com/go/datasheet/offices. Speed (ns) Ordering Code 12 CY7C1021BN-12ZXC 15 CY7C1021BNL-15VXC CY7C1021BN-15ZXC CY7C1021BN-15ZXI CY7C1021BNL-15ZXI CY7C1021BNL-15ZSXA CY7C1021BN-15VXE CY7C1021BN-15ZSXE Ordering Code Definition Technology: 250 nm Speed = ns; without ns Bus Width: x16 ...

Page 11

Package Diagrams Document #: 001-06494 Rev. *C CY7C1021BN, CY7C10211BN Figure 8. 44-Pin (400-Mil) Molded SOJ Figure 9. 44-Pin TSOP II 51-85082 *C 51-85087 *C Page [+] Feedback ...

Page 12

Acronyms Table 1. Acronyms Used in this Document Acronym Description BHE Byte high enable BLE Byte low enable CE Chip enable CMOS Complementary metal oxide semiconductor I/O Input/output OE Output enable SRAM Static random access memory TSOP Thin small outline ...

Page 13

... Corrected ‘Byte write select inputs’ to ‘Byte Enable select inputs’ on page 2. Ω Added ohm ( )symbol inThevenin equivalent circuit on page 4. Included T and T to Switching Characteristics table footnote 2 HZBE LZBE Included operating range for CY7C1021BNL-15ZXI in ordering information table. cypress.com/go/plc Revised June 11, 2010 CY7C1021BN, CY7C10211BN PSoC Solutions psoc.cypress.com/solutions PSoC 1 | PSoC 3 ...

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