CY7C135-25JXI Cypress Semiconductor Corp, CY7C135-25JXI Datasheet - Page 7

• Manufacturer Part Number: CY7C135-25JXI
• Description: CY7C135-25JXI
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C135-25JXI

• Format - Memory: RAM
• Memory Type: SRAM - Dual Port, Asynchronous
• Memory Size: 32K (4K x 8)
• Speed: 25ns
• Interface: Parallel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 52-PLCC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Switching Waveforms
Document #: 38-06038 Rev. *D
Notes
16. The internal write time of the memory is defined by the overlap of CE or SEM LOW and R/W LOW. Both signals must be LOW to initiate a write and either signal
17. R/W must be HIGH during all address transactions.
18. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of t
19. Data I/O pins enter high impedance when OE is held LOW during write.
can terminate a write by going HIGH. The data input setup and hold timing should be referenced to the rising edge of the signal that terminates the write.
to be placed on the bus for the required t
write pulse can be as short as the specified t
ADDRESS
ADDRESS
DATA
DATA
SEM
DATA
SEM
DATA
OR CE
OR CE
R/W
OUT
R/W
OUT
OE
[11]
IN
IN
[11]
Figure 7. Write Cycle No. 1: OE Three-States Data I/Os (Either Port)
Figure 8. Write Cycle No. 2: R/W Three-States Data I/Os (Either Port)
t
SA
(continued)
SD
. If OE is HIGH during a R/W controlled write cycle (as in this example), this requirement does not apply and the
PWE
t
SA
t
HZOE
.
t
SCE
t
t
AW
SCE
t
HIGH IMPEDANCE
t
AW
HZWE
t
WC
t
WC
t
PWE
t
PWE
PWE
t
SD
DATA VALID
t
HIGH IMPEDANCE
or (t
SD
DATA VALID
HZWE
+ t
SD
) to allow the I/O drivers to turn off and data
[16, 17, 18]
t
t
CY7C135, CY7C135A
t
HD
LZWE
HA
[17, 19]
t
LZOE
t
HA
t
HD
CY7C1342
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