CY7C1412AV18-200BZI Cypress Semiconductor Corp, CY7C1412AV18-200BZI Datasheet
CY7C1412AV18-200BZI
Specifications of CY7C1412AV18-200BZI
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CY7C1412AV18-200BZI Summary of contents
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... To maximize data throughput, both read and write ports are provided with DDR interfaces. Each address location is associated with two 18 bit words (CY7C1412AV18 bit words (CY7C1414AV18) that burst sequentially into or out of the device. Because data can be transferred into and out of the ...
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... Logic Block Diagram – CY7C1412AV18 18 D [17:0] 20 Address A (19:0) Register K CLK K Gen. DOFF V REF Control WPS Logic BWS [1:0] Logic Block Diagram – CY7C1414AV18 36 D [35:0] 19 Address A (18:0) Register K CLK K Gen. DOFF V REF Control WPS Logic BWS [3:0] Document #: 38-05615 Rev. *H ...
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... Pin Configuration The pin configuration for CY7C1412AV18, and CY7C1414AV18 follow. 165-Ball FBGA ( 1.4 mm) Table 1. CY7C1412AV18 ( NC/144M D10 D NC D11 Q10 Q11 F NC Q12 D12 G NC D13 Q13 H DOFF V V REF DDQ D14 Q14 L NC Q15 D15 D16 N NC D17 Q16 ...
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... Synchronous active read and write operations. These address inputs are multiplexed for both read and write operations. Internally, the device is organized arrays each 18) for CY7C1412AV18 and arrays each of 512K x 36) for CY7C1414AV18. Therefore, only 20 address inputs are needed to access the entire memory array of CY7C1412AV18 and 19 address inputs for CY7C1414AV18. These inputs are ignored when the appropriate port is deselected ...
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... Reference Voltage Input. Static input used to set the reference level for HSTL inputs, outputs, and AC REF Reference measurement points. V Power Supply Power Supply Inputs to the Core of the Device Ground Ground for the Device Power Supply Power Supply Inputs for the Outputs of the Device. DDQ Document #: 38-05615 Rev. *H CY7C1412AV18 CY7C1414AV18 Pin Description Page [+] Feedback ...
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... Each access consists of two 18 bit data transfers in the case of CY7C1412AV18, and two 36 bit data transfers in the case of CY7C1414AV18 in one clock cycle. Accesses for both ports are initiated on the rising edge of the positive input clock (K) ...
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... The DLL automatically locks 1024 clock cycles after a stable clock is presented. The DLL may be disabled by applying ground to the DOFF pin. For information refer to the application note QDRII/DDRII/QDRII+/DDRII+. Figure 1. Application Example SRAM # 250ohms CQ/CQ Vddq/2 CY7C1412AV18 CY7C1414AV18 AN5062, DLL Considerations in SRAM # 250ohms CQ/CQ ...
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... Truth Table The truth table for CY7C1412AV18, and CY7C1414AV18 follows. Operation Write Cycle: Load address on the rising edge of K; input write data on K and K rising edges. Read Cycle: Load address on the rising edge of K; wait one and a half cycle; read data on C and C rising edges. ...
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... L–H During the Data portion of a write sequence, only the byte (D the device. D remains unaltered. [26:0] – No data is written into the device during this portion of a write operation. L–H No data is written into the device during this portion of a write operation. CY7C1412AV18 CY7C1414AV18 ) are written into [35:0] ) are written into [35: written ...
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... TAP controller must be moved into the Update-IR state. IDCODE The IDCODE instruction loads a vendor-specific, 32 bit code into the instruction register. It also places the instruction register CY7C1412AV18 CY7C1414AV18 ) when SS on page 16 shows the order in which Identification Register Definitions ...
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... The shifting of data for the SAMPLE and PRELOAD phases can occur concurrently when required, that is, while the data captured is shifted out, the preloaded data can be shifted in. Document #: 38-05615 Rev. *H CY7C1412AV18 CY7C1414AV18 BYPASS When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift-DR state, the bypass register is placed between the TDI and TDO pins ...
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... IDLE Note 9. The 0/1 next to each state represents the value at TMS at the rising edge of TCK. Document #: 38-05615 Rev. *H [9] 1 SELECT DR-SCAN 0 1 CAPTURE- SHIFT- EXIT1- PAUSE- EXIT2-DR 1 UPDATE- CY7C1412AV18 CY7C1414AV18 1 SELECT IR-SCAN 0 1 CAPTURE- SHIFT- EXIT1- PAUSE- EXIT2-IR 1 UPDATE- Page [+] Feedback ...
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... Boundary Scan Register TAP Controller Test Conditions I =2 =100 2 100 GND V /2), Undershoot: V (AC) > 1.5V (Pulse width less than t CYC IL CY7C1412AV18 CY7C1414AV18 Selection TDO Circuitry Min Max Unit 1.4 V 1.6 V 0.4 V 0.2 V 0.65V –0.3 0.35V V DD ...
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... Test conditions are specified using the load in TAP AC Test Conditions. t Document #: 38-05615 Rev. *H Description [14] Figure 2. TAP Timing and Test Conditions 0.9V 1.8V 50 TMSH t TMSS t TDIS t TDIH t TDOV / ns CY7C1412AV18 CY7C1414AV18 Min Max Unit 50 20 MHz ALL INPUT PULSES 0.9V t TCYC t TDOX Page ...
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... Places the bypass register between TDI and TDO. This operation does not affect SRAM operation. Document #: 38-05615 Rev. *H Value CY7C1414AV18 000 000 11010011010100111 00000110100 00000110100 1 Description CY7C1412AV18 CY7C1414AV18 Description Version number. Defines the type of SRAM. Allows unique identification of SRAM vendor. 1 Indicates the presence register. Bit Size 3 ...
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... Bump ID Bit # Bump ID 10G 11F 58 5A 11G 10F 61 4B 11E 62 3A 10E 63 2A 10D 10C 66 3B 11D 11B 70 3C 11C 10B 73 3E 11A 74 2D 10A CY7C1412AV18 CY7C1414AV18 Bit # Bump 100 2P 101 1P 102 3R 103 4R 104 4P 105 5P 106 5N 107 5R 108 Internal Page [+] Feedback ...
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... DLL may lock onto an incorrect frequency, causing unstable SRAM behavior. To avoid this, provide1024 cycles stable clock to relock to the desired clock frequency. . REF Figure 3. Power Up Waveforms > 1024 Stable clock Stable DDQ Stable (< +/- 0.1V DC per 50ns ) / DDQ Fix High (or tie to V DDQ ) CY7C1412AV18 CY7C1414AV18 . KC Var Start Normal Operation Page [+] Feedback ...
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... During this time V < V and /2)/(RQ/5) for values of 175 ohms <= RQ <= 350 ohms. (max) = 0.95V or 0.54V , whichever is smaller. REF DDQ CY7C1412AV18 CY7C1414AV18 Test Con- Description Typ Max* ditions Logical 25°C 320 368 Single Bit Upsets Logical Multi 25° ...
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... DD Both Ports Deselected, (x36) V 200MHz (x18 1/t , MAX CYC Inputs Static (x36) 167MHz (x18) (x36) Test Conditions CY7C1412AV18 CY7C1414AV18 Min Typ Max Unit 420 mA 475 370 420 345 390 Min Typ Max Unit V + 0.2 – – V REF – ...
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... REF V 0.75V R = 50 REF OUTPUT Device 0.25V 5 pF Under ZQ Test RQ = 250 INCLUDING JIG AND (b) SCOPE /I and load capacitance shown in ( CY7C1412AV18 CY7C1414AV18 Max Unit = 1. DDQ 165 FBGA Unit Package 17.2 °C/W 3.2 °C/W [20] ALL INPUT PULSES 1.25V 0.75V Slew Rate = 2 V/ ...
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... DLL Lock Time ( lock KC lock Static to DLL Reset KC Reset KC Reset Document #: 38-05615 Rev. *H Description [22] , BWS ) BWS ) 3 4 [24, 25] [24, 25] CY7C1412AV18 CY7C1414AV18 250 MHz 200 MHz 167 MHz Unit Min Max Min Max Min Max 4.0 8.4 5.0 8.4 6.0 8.4 ns 1.6 – 2.0 – ...
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... DD is 0.5 ns for 200 MHz, and 250 MHz frequencies Test Loads and Waveforms and t less than t . CLZ CHZ CO CY7C1412AV18 CY7C1414AV18 250 MHz 200 MHz 167 MHz Min Max Min Max Min Max 4.0 8.4 5 ...
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... In this example, if address A0 = A1, then data Q00 = D10 and Q01 = D11. Write data is forwarded immediately as read results. This note applies to the whole diagram. Document #: 38-05615 Rev. *H WRITE WRITE READ NOP KHKH t CYC D31 D50 D51 D60 Q00 Q01 Q20 t CLZ t CQDOH t DOH CYC t CCQO t CQOH t CCQO CY7C1412AV18 CY7C1414AV18 [26, 27, 28] WRITE NOP D61 Q21 Q40 Q41 t CHZ t CQD DON’T CARE UNDEFINED Page [+] Feedback ...
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... C = Commercial Industrial Package Type: XXX = BZX or BZ BZX = 165-ball FPBGA (Pb-free 165-ball FPBGA Speed: XXX = 250 MHz / 200 MHz / 167 MHz V18 = 1.8 V Process Technology Errata affected part Part Identifier CY7C = Cypress SRAMs CY7C1412AV18 CY7C1414AV18 Operating Range Industrial Industrial Page [+] Feedback ...
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... Package Diagram Document #: 38-05615 Rev. *H Figure 6. 165-ball FBGA (15 × 17 × 1.4 mm) CY7C1412AV18 CY7C1414AV18 51-85195 *B Page [+] Feedback ...
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... Document History Page Document Title: CY7C1412AV18/CY7C1414AV18, 36 Mbit QDR Document Number: 38-05615 Orig. of Submission Revision ECN Change ** 247331 SYT See ECN *A 326519 SYT See ECN *B 413953 NXR See ECN *C 468029 NXR See ECN *D 1274725 VKN/AESA See ECN Document #: 38-05615 Rev. *H ® II SRAM Two Word Burst Architecture ...
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... Document History Page Document Title: CY7C1412AV18/CY7C1414AV18, 36 Mbit QDR Document Number: 38-05615 *E 2511746 VKN/AESA See ECN *F 2755901 VKN 08/25/09 *G 2897278 NJY 03/22/2010 *H 3101004 NJY 12/03/2010 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at cypress ...