CY7C68013A-56LTXI Cypress Semiconductor Corp, CY7C68013A-56LTXI Datasheet - Page 40

• Manufacturer Part Number: CY7C68013A-56LTXI
• Description: CY7C68013A-56LTXI
• Manufacturer: Cypress Semiconductor Corp
• Series: EZ-USB FX2LP™r

Specifications of CY7C68013A-56LTXI

• Applications: USB Microcontroller
• Core Processor: 8051
• Program Memory Type: ROMless
• Controller Series: CY7C680xx
• Ram Size: 16K x 8
• Interface: I²C, USB, USART
• Number Of I /o: 24
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 56-VQFN Exposed Pad, 56-HVQFN, 56-SQFN, 56-DHVQFN
• Cpu Family: FX2LP
• Device Core: 8051
• Device Core Size: 8b
• Frequency (max): 48MHz
• Interface Type: I2C/USART/USB
• Program Memory Size: Not Required
• Total Internal Ram Size: 16KB
• # I/os (max): 24
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 105C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 56
• Package Type: QFN EP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CY4611B - KIT USB TO ATA REFERENCE DESIGN428-1677 - KIT DEVELOPMENT EZ-USB FX2LP
• Lead Free Status / Rohs Status: Compliant

10.4 Data Memory Write
Table 17. Data Memory Write Parameters
When using the AUTPOPTR1 or AUTOPTR2 to address external memory, the address of AUTOPTR1 is only active while either RD#
or WR# are active. The address of AUTOPTR2 is active throughout the cycle and meets the above address valid time for which is
based on the stretch value.
Document #: 38-08032 Rev. *M
t
t
t
t
t
t
AV
STBL
STBH
SCSL
ON1
OFF1
CLKOUT
CLKOUT
Parameter
A[15..0]
A[15..0]
D[7..0]
D[7..0]
CS#
WR#
CS#
WR#
t
t
AV
AV
Delay from Clock to Valid Address
Clock to WR Pulse LOW
Clock to WR Pulse HIGH
Clock to CS Pulse LOW
Clock to Data Turn-on
Clock to Data Hold Time
t
t
CL
CL
t
SCSL
t
ON1
t
ON1
t
STBL
Description
Figure 14. Data Memory Write Timing Diagram
data out
Stretch = 1
data out
t
STBH
Min
0
0
0
0
0
t
t
OFF1
AV
CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
Max
10.7
13.0
13.1
11.2
11.2
13.1
Unit
ns
ns
ns
ns
ns
ns
Page 40 of 62
t
OFF1
Notes
[+] Feedback