EP9307-CRZR Cirrus Logic Inc, EP9307-CRZR Datasheet - Page 2

• Manufacturer Part Number: EP9307-CRZR
• Description: IC Universal Platform ARM9 SOC Prcessor
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9307-CRZR

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LCD, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 14
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 272-LFBGA
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: EDB9307A-Z
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: Q5809834A

Analog Touch Screen
Ethernet
2
Description
After power-on-reset, PENSTS in AR_SETUP2 register has the correct default value of “0”. But after the first
touch on the screen, PENSTS is stuck at “1” regardless if the screen is pressed or not.
Workaround
Configure the hardware so that as long as there is pressure on the touch surface, interrupts will occur
periodically. This is done by setting the register ARXYMAXMIN so that the MIN values are 0x0 and the MAX
values are 0xff. This causes the hardware to believe that while there is pressure on the surface, the pointing
device is always moving. The frequency of interrupts is programmable in TSSETUP by adjusting the settling
times and number of samples taken for each point. If a touch event takes longer than this time to occur, it
is assumed that the touch surface has been released. For an example of this implementation, please see
the source code provided with our Linux and WinCE Touch Screen drivers.
Description 1
The Ethernet controller does not correctly receive frames that have a size of 64 bytes.
Workaround
In order to receive frames of 64 bytes, enable the RCRCA bit in RxCTL. This will prevent the Ethernet
controller from discarding the 64-byte-long frames.
Description 2
When there is inadequate AHB bus bandwidth for data to be transferred from the Ethernet controller FIFO
to the receive descriptor, the Ethernet FIFO will overflow and cause the Ethernet controller to fail to receive
any more packets.
This problem will also occur if the processor is too busy to service incoming packets in a timely manner. By
the time that new receive descriptors are available, the data in the FIFO will contain frames that are
corrupted.
It is the job of the system designer to ensure that there is adequate bandwidth for the applications being run.
Workaround
This is a rare occurrence, however at a system level it is important to reserve adequate bandwidth for the
Ethernet controller. This can be accomplished by some of the following:
- Reducing the bandwidth use of other bus masters in the system.
- Lowering Ethernet rate to half duplex or 10Mbit if higher bandwidth is not required.
- Ensuring that the Ethernet controller receive descriptor processing is given a high enough priority to
ensure that the controller never runs out of receive descriptors.
ER667E2B