EVAL-ADV7173EBZ Analog Devices Inc, EVAL-ADV7173EBZ Datasheet - Page 37

• Manufacturer Part Number: EVAL-ADV7173EBZ
• Description: EVALUATION BOARD
• Manufacturer: Analog Devices Inc
• Series: Advantiv®r

Specifications of EVAL-ADV7173EBZ

• Main Purpose: Video, Video Processing
• Embedded: No
• Utilized Ic / Part: ADV7173
• Primary Attributes: NTSC/PAL Digital Video Encoder
• Secondary Attributes: I²C Interface
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

TELETEXT REQUEST CONTROL REGISTER TC07
(TC07–TC00)
(Address (SR4–SR0) = 1CH)
Teletext Control Register is an 8-bit-wide register. See Figure 59.
TTXREQ Rising Edge Control (TC07–TC04)
These bits control the position of the rising edge of TTXREQ.
It can be programmed from zero CLOCK cycles to a max of 15
CLOCK cycles.
TTXREQ Falling Edge Control (TC03–TC00)
These bits control the position of the falling edge of TTXREQ.
It can be programmed from zero CLOCK cycles to a max of 15
CLOCK cycles. This controls the active window for Teletext
data. Increasing this value reduces the amount of Teletext Bits
below the default of 360. If Bits TC03–TC00 are 00Hex when
Bits TC07–TC04 are changed, then the falling edge of TTXREQ
will track that of the rising edge (i.e., the time between the fall-
ing and rising edge remains constant).
CGMS_WSS REGISTER 0 C/W0 (C/W07–C/W00)
(Address (SR4–SR0) = 19H)
CGMS_WSS Register 0 is an 8-bit-wide register. Figure 60
shows the operations under control of this register.
C/W07
WIDE SCREEN SIGNAL
0
1
CONTROL
TC07
DISABLE
ENABLE
TC07 TC06
0
0
"
1
1
C/W07
TTXREQ RISING EDGE CONTROL
C/W06
CGMS EVEN FIELD
0
0
"
1
1
0
1
TC06
CONTROL
TC05 TC04
C/W06
0
0
"
1
1
DISABLE
ENABLE
C/W05
CGMS ODD FIELD
0
1
0
1
"
0
1
TC05
CONTROL
C/W05
DISABLE
ENABLE
0 PCLK
1 PCLK
" PCLK
14 PCLK
15 PCLK
C/W04
CGMS CRC CHECK
0
1
TC04
CONTROL
C/W04
DISABLE
ENABLE
C/W BIT DESCRIPTION
CGMS Data (C/W03–C/W00)
These four data bits are the final four bits of CGMS data out-
put stream. Note it is CGMS data ONLY in these bit positions
i.e., WSS data does not share this location.
CGMS CRC Check Control (C/W04)
When this bit is enabled (“1”), the last six bits of the CGMS
data, i.e., the CRC check sequence, are calculated internally by
the ADV7172/ADV7173. If this bit is disabled (“0”), the CRC
values in the register are output to the CGMS data stream.
CGMS Odd Field Control (C/W05)
When this bit is set (“1”), CGMS is enabled for odd fields.
Note that this is only valid in NTSC mode.
CGMS Even Field Control (C/W06)
When this bit is set (“1”), CGMS is enabled for even fields.
Note that this is only valid in NTSC mode.
Wide Screen Signal Control (C/W07)
When this bit is set (“1”), wide screen signalling is enabled.
Note that this is only valid in PAL mode.
TC03
TC03 TC02
0
0
"
1
1
TTXREQ FALLING EDGE CONTROL
C/W03
0
0
1
1
"
TC02
TC01 TC00
C/W02
0
0
1
1
"
C/W03–C/W00
CGMS DATA
0
1
"
0
1
TC01
C/W01
0 PCLK
1 PCLK
" PCLK
14 PCLK
15 PCLK
TC00
ADV7172/ADV7173
C/W00