LTC2704IGW-16 Linear Technology, LTC2704IGW-16 Datasheet - Page 11

• Manufacturer Part Number: LTC2704IGW-16
• Description: IC,D/A CONVERTER,QUAD,16-BIT,CMOS,SOP,44PIN
• Manufacturer: Linear Technology

OPERATIO
SERIAL INTERFACE
When the CS/LD pin is taken low, the data on the SDI pin
is loaded into the shift register on the rising edge of the
clock signal (SCK pin). The minimum (24-bit wide) load-
ing sequence required for the LTC2704 is a 4-bit com-
mand word (C3 C2 C1 C0), followed by a 4-bit address
word (A3 A2 A1 A0) and 16 data (span or code) bits, MSB
first. Figure 1 shows the SDI input word syntax to use
when writing a code or span. If a 32-bit input sequence is
needed, the first eight bits must be zeros, followed by the
same sequence as for a 24-bit wide input. Figure 2 shows
the input and readback sequences for both 24-bit and
32-bit operations.
When CS/LD is low, the Serial Readback Output (SRO) pin
is an active output. The readback data begins after the
command (C3-C0) and address (A3-A0) words have been
shifted into SDI. For a 24-bit load sequence, the 16
readback bits are shifted out on the falling edges of clocks
8-23, suitable for shifting into a microprocessor on the
rising edges of clocks 9-24. For a 32-bit load sequence,
add 8 to these clock cycle counts; see Figure 2b.
When CS/LD is high, the SRO pin presents a high imped-
ance (three-state) output. At the beginning of a load
sequence, when CS/LD is taken low, SRO outputs a logic
low until the readback data begins.
When the asynchronous load pin, LDAC, is taken low, all
DACs are updated with code and span data (data in B1
buffers is copied into B2 buffers). CS/LD must be high
during this operation. The use of LDAC is functionally
identical to the “Update B1→B2” commands.
The codes for the command word (C3-C0) are defined in
Table 1; Table 2 defines the codes for the address word
(A3-A0).
READBACK
Each DAC has two pairs of double-buffered digital regis-
ters, one pair for DAC code and the other for the output
span (four buffers per DAC). Each double-buffered pair
comprises two registers called buffer 1 (B1) and buffer 2
(B2).
U
B1 is the holding buffer. When data is shifted into B1 via
a write operation, DAC outputs are not affected. The
contents of B2 can only be changed by copying the
contents of B1 into B2 via an update operation (B1 and B2
can be changed together, see commands 0110-1001 in
Table 1). The contents of B2 (DAC code or DAC span)
directly control the DAC output voltage or the DAC output
range.
Additionally each DAC has one readback register associ-
ated with it. When a readback command is issued to a DAC,
the contents of one of its four buffers is copied into its
readback register and serially shifted out onto the SRO pin.
Figure 2 shows the loading and readback sequences. In
the 16-bit data field (D15-D0 for the LTC2704-16, see
Figure 2a) of any write or update command, the readback
pin (SRO) shifts out the contents of the buffer which was
specified in the preceding command. This “rolling
readback” mode of operation can be used to reduce the
number of operations, since any command can be verified
during succeeding commands with no additional over-
head. Table 1 shows the location (readback pointer) of the
data which will be output from SRO during the next
instruction.
For readback commands, the data is shifted out during the
readback instruction itself (on the 16 falling SCK edges
immediately after the last address bit is shifted in on SDI).
When programming the span of a DAC, the span bits are
the last four bits shifted in; and when checking the span of
a DAC using SRO, the span bits are likewise the last four
bits shifted out. Table 3 shows the span codes.
When span information is read back on SRO, the sleep
status of the addressed DAC is also output. The sleep
status bit, SLP, occurs sequentially just before the four
span bits. The sequence is shown in Figures 2a and 2b. See
Table 4 for SLP codes. Note that SLP is an output bit only;
sleep is programmed by using command code 1110 along
with the desired address. Any update command, including
the use of LDAC, wakes the addressed DAC(s).
LTC2704
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