LTC6900CS5 Linear Technology, LTC6900CS5 Datasheet - Page 6

• Manufacturer Part Number: LTC6900CS5
• Manufacturer: Linear Technology
• Type: Silicon Oscillatorr

Specifications of LTC6900CS5

• Mounting Style: Surface Mount
• Screening Level: Industrial
• Product Length (mm): 2.9mm
• Product Depth (mm): 1.75mm
• Product Height (mm): 0.9mm
• Package / Case: TSOT-23
• Lead Free Status / RoHS Status: Not Compliant

THEORY OF OPERATIO
LTC6900
As shown in the Block Diagram, the LTC6900’s master
oscillator is controlled by the ratio of the voltage between
the V
SET pin. The voltage on the SET pin is forced to approxi-
mately 1.1V below V
bias voltage. This voltage is accurate to 8% at a particular
input current and supply voltage (see Figure 1).
A resistor R
“locks together” the voltage (V
variation. This provides the LTC6900’s high precision. The
master oscillation frequency reduces to:
The LTC6900 is optimized for use with resistors between
10k and 2M, corresponding to master oscillator frequen-
cies between 100kHz and 20MHz.
To extend the output frequency range, the master oscilla-
tor signal may be divided by 1, 10 or 100 before driving
OUT (Pin 5). The divide-by value is determined by the state
of the DIV input (Pin 4). Tie DIV to GND or drive it below
6
MO
+
and SET pins and the current (I
10
1.4
1.3
1.2
1.1
1.0
0.9
0.8
Figure 1. V
SET
0.1
MHz
, connected between the V
•
V
+
1
+
20
R
+
by the PMOS transistor and its gate
= 3V
SET
– V
k
I
SET
RES
V
+
10
= 5V
( A)
Variation with I
+
– V
100
SET
RES
) and current, I
U
6900 F01
) is entering the
+
1000
RES
and SET pins,
RES
,
0.5V to select 1. This is the highest frequency range, with
the master output frequency passed directly to OUT. The
DIV pin may be floated or driven to midsupply to select
quency range, 100, is selected by tying DIV to V
driving it to within 0.4V of V
ship between R
including the overlapping frequency ranges near 100kHz
and 1MHz.
The CMOS output driver has an on resistance that is
typically less than 100 . In the 1 (high frequency) mode,
the rise and fall times are typically 7ns with a 5V supply and
11ns with a 3V supply. These times maintain a clean
square wave at 10MHz (20MHz at 5V supply). In the 10
and 100 modes, where the output frequency is much
lower, slew rate control circuitry in the output driver
increases the rise/fall times to typically 14ns for a 5V
supply and 19ns for a 3V supply. The reduced slew rate
lowers EMI (electromagnetic interference) and supply
bounce.
10, the intermediate frequency range. The lowest fre-
10000
1000
Figure 2. R
100
10
1
1k
SET
DESIRED OUTPUT FREQUENCY (Hz)
10k
100
, divider setting and output frequency,
SET
vs Desired Output Frequency
100k
10
+
. Figure 2 shows the relation-
1M
1
10M
6900 F02
100M
+
6900f
or