FDSS2407 Fairchild Semiconductor, FDSS2407 Datasheet

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FDSS2407

Manufacturer Part Number
FDSS2407
Description
MOSFET N-CH 62V 3.3A 8-SOIC
Manufacturer
Fairchild Semiconductor
Datasheet

Specifications of FDSS2407

Fet Type
2 N-Channel (Dual)
Fet Feature
Logic Level Gate
Rds On (max) @ Id, Vgs
110 mOhm @ 3.3A, 10V
Drain To Source Voltage (vdss)
62V
Current - Continuous Drain (id) @ 25° C
3.3A
Vgs(th) (max) @ Id
3V @ 250µA
Gate Charge (qg) @ Vgs
4.3nC @ 5V
Input Capacitance (ciss) @ Vds
300pF @ 15V
Power - Max
2.27W
Mounting Type
Surface Mount
Package / Case
8-SOIC (3.9mm Width)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
©2004 Fairchild Semiconductor Corporation
FDSS2407 Rev. A
FDSS2407
62V, 3.3A, 132mΩ
Features
Applications
N-Channel Dual MOSFET
62V, 132mΩ, 5V Logic Level Gate Dual MOSFET in SO-8
5V Logic Level feedback signal of the drain to source
voltage. Multiple devices can be wired “OR’d” to a single
monitoring circuit input.
Gate Drive Disable Input. Multiple devices controllable by
a single disable transistor.
Qualified to AEC Q101
Automotive Injector Driver
Solenoid Driver
Branding Dash
Pin 5 - Drain Feedback Output
Pin 7 - Gate Drive Disable Input
1
2
3
4
SO-8
5
Source 2
Source 1
Gate 2
Gate 1
1
2
3
4
1
General Description
This dual N-Channel MOSFET provides added functions as
compared to a conventional Power MOSFET. These are: 1.
A drain to source voltage feedback signal and 2. A gate
drive disable control function that previously required
external discrete circuitry. Including these functions within
the MOSFET saves printed circuit board space. The drain to
source voltage feedback function provides a 5V level output
whenever the drain to source voltage is above 62V. This can
monitor the time an inductive load takes to dissipate its
stored energy. Multiple feedback signals can be wired
“OR’d” together to a single input of the monitoring circuit.
The gate disable function allows the device to be turned off
independent of the drive signal on the gate. This function
permits a second control circuit the ability to deactivate the
load if necessary. It can also be wired “OR’d” allowing
multiple devices to be controlled by a single open collector /
drain control transistor.
Internal Diagram
December 2004
8
7
6
5
www.fairchildsemi.com
Drain 1
Gate Disable
Drain 2
Drain FBK

Related parts for FDSS2407

FDSS2407 Summary of contents

Page 1

... SO-8 Pin 5 - Drain Feedback Output Pin 7 - Gate Drive Disable Input ©2004 Fairchild Semiconductor Corporation FDSS2407 Rev. A General Description This dual N-Channel MOSFET provides added functions as compared to a conventional Power MOSFET. These are drain to source voltage feedback signal and 2. A gate drive disable control function that previously required external discrete circuitry ...

Page 2

... Reverse Transfer Capacitance RSS R Gate Resistance G Q Total Gate Charge at 5V g(TOT) Q Threshold Gate Charge g(TH) Q Gate to Source Gate Charge gs Q Gate Charge Threshold to Plateau gs2 Q Gate to Drain “Miller” Charge gd FDSS2407 Rev =25°C unless otherwise noted A Parameter 10V C/W) θ 5V C/W) θ ...

Page 3

... This product has been designed to meet the extreme test conditions and environment demanded by the automotive industry. For a copy of the requirements, see AEC Q101 at: http://www.aecouncil.com/ All Fairchild Semiconductor products are manufactured, assembled and tested under ISO9000 and QS9000 quality systems FDSS2407 Rev 10V) ...

Page 4

... Figure 3. Normalized Maximum Transient Thermal Impedance 200 TRANSCONDUCTANCE 100 MAY LIMIT CURRENT IN THIS REGION 10V FDSS2407 Rev 25°C unless otherwise noted 100 125 150 Figure 2. Maximum Continuous Drain Current vs SINGLE PULSE - RECTANGULAR PULSE DURATION ( θ ...

Page 5

... PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX 210 I = 3.3A D 180 150 120 GATE TO SOURCE VOLTAGE (V) GS Figure 9. Drain to Source On Resistance vs Gate Voltage and Drain Current FDSS2407 Rev. A (Continued 25°C unless otherwise noted A 10 100µs 1ms STARTING T 10ms ≠ C/W t θ ...

Page 6

... DRAIN TO SOURCE VOLTAGE (V) DS Figure 13. Feedback Voltage vs Drain to Source Voltage 500 400 300 200 100 GATE DISABLE VOLTAGE (V) DIS Figure 15. Drain to Source On Resistance vs Gate Disable Voltage FDSS2407 Rev. A (Continued 25°C unless otherwise noted A 1 250µ 1.1 1.0 0.9 80 120 160 ...

Page 7

... Figure 17. Gate Charge Waveforms for Constant Gate Currents Test Circuits and Waveforms VARY t TO OBTAIN P R REQUIRED PEAK Figure 18. Unclamped Energy Test Circuit g(REF) Figure 20. Gate Charge Test Circuit FDSS2407 Rev. A (Continued 25°C unless otherwise noted 30V WAVEFORMS IN 2 DESCENDING ORDER ...

Page 8

... Test Circuits and Waveforms Figure 22. Switching Time Test Circuit V DISABLE Figure 24. Gate to Source Voltage vs Gate Disable Voltage FDSS2407 Rev. A (Continued d(ON 90 DUT V GS 50% 10% 0 Figure 23. Switching Time Waveforms LM324 - DUT OFF t d(OFF 10% 10% 90% 50% PULSE WIDTH NC www.fairchildsemi.com 90% ...

Page 9

... Figure 26. Thermal Impedance vs Mounting Pad Area FDSS2407 Rev and the maximum transient thermal impedance curve. JM Thermal resistances corresponding to other copper areas , can be obtained from Figure calculation using application’s ambient o Equation 2. The area, in square inches is the top copper ...

Page 10

... PSPICE Electrical Model .SUBCKT FDSS2407 101 102 1e- 4e-10 Cin 6 8 2.8e-10 Dbody 7 5 DbodyMOD Dbreak 5 11 DbreakMOD Dplcap 10 5 DplcapMOD CGATE 9 20 5e-9 DDISABLE 20 101 DDISABLEMOD DFBK1 104 103 DFBK1MOD DFBK2 7 104 DFBK2MOD DFBK3 104 102 DFBK3MOD RFBK1 5 103 RFBK1MOD 13e3 RFBK2 104 7 RFBK2MOD 2 ...

Page 11

... FDSS2407 Rev. A DPLCAP RSLC2 - 6 ESG 8 EVTHRES ...

Page 12

... FDSS2407 Rev. A JUNCTION th RTHERM1 8 RTHERM2 7 RTHERM3 6 RTHERM4 5 RTHERM5 ...

Page 13

... PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Advance Information Preliminary No Identification Needed Obsolete FDSS2407 Rev. A ImpliedDisconnect™ POP™ IntelliMAX™ Power247™ ISOPLANAR™ PowerEdge™ LittleFET™ PowerSaver™ ...

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