MX7575JP Maxim Integrated Products, MX7575JP Datasheet - Page 7

• Manufacturer Part Number: MX7575JP
• Description: Audio A/D Converter ICs
• Manufacturer: Maxim Integrated Products

Specifications of MX7575JP

• Conversion Rate: 200 KSPs
• Resolution: 8 bit
• Number Of Adc Inputs: 1
• Operating Supply Voltage: 5 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Supply Voltage (max): 5.25 V
• Supply Voltage (min): 4.75 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

the µP, in that data can be accessed independently of
the clock. The output latches are normally updated on
the rising edge of BUSY. But if CS and RD are low
when BUSY goes high, the data latches are not updat-
ed until one of these inputs returns high. Additionally,
the MX7576 stops converting and BUSY stays high until
RD or CS goes high. This mode of operation allows a
simple interface to the µP.
In many applications, it is necessary to sample the
input signal at exactly equal intervals to minimize errors
due to sampling uncertainty or jitter. In order to achieve
this objective with the previously discussed interfaces,
the user must match software delays or count the num-
ber of elapsed clock cycles. This becomes difficult in
interrupt-driven systems where the uncertainty in inter-
rupt servicing delays is another complicating factor.
The solution is to use a real-time clock to control the
start of a conversion. This should be synchronous with
Figure 7. MX7575/MX7576 to Z-80 ROM Interface
Figure 8. MX7575/MX7576 to TMS32010 ROM Interface
Processor Interface for Signal Acquisition (MX7575)
* SOME CIRCUITRY OMITTED FOR CLARITY
TMS32010
* SOME CIRCUITRY OMITTED FOR CLARITY
Z-80
MEN
DEN
DB7
DB0
PA2
PA0
MREQ
CMOS, µP-Compatible, 5µs/10µs, 8-Bit ADCs
DB7
DB0
RD
_______________________________________________________________________________________
EN
ADDRESS BUS
EN
DATA BUS
ADDRESS
DECODE
ADDRESS BUS
DATA BUS
ADDRESS
DECODE
+5V
+5V
TP/MODE
CS
RD
D7
D0
TP/MODE
CS
RD
D7
D0
MX7576
MX7575*
MX7576
MX7575*
the CLK input to the ADC (both should be derived from
the same source), because the sampling instants occur
three clock cycles after CS and RD go low. Therefore,
the sampling instants occur at exactly equal intervals if
the conversions are started at equal intervals. In this
scheme, the output data is fed into a FIFO latch, which
allows the µP to access data at its own rate. This guar-
antees that data is not read from the ADC in the middle
of a conversion. If data is read from the ADC during a
conversion, the conversion in progress may be dis-
turbed, but the accessed data that belonged to the pre-
vious conversion will be correct.
The track/hold starts holding the input on the third
falling edge of the clock after CS and RD go low. If CS
and RD go low within 20ns of a falling clock edge, the
ADC may or may not consider this falling edge as the
first of the three edges that determine the sampling
instant. Therefore, the CS and RD should not be
allowed to go low within this period when sampling
accuracy is required.
Figure 9. MX7576 Asynchronous Conversion Mode Timing
Diagram
Figure 10. MX7576 to 8085A Asynchronous Conversion Mode
Interface
BUSY
DATA
CS
RD
* SOME CIRCUITRY OMITTED FOR CLARITY
IMPEDANCE
8085A
AD0–AD7
HIGH-
A0–A15
BUS
t
1
t
ALE
3
RD
VALID
DATA
t
4
ADDRESS
LATCH
HIGH-IMPEDANCE BUS
ADDRESS BUS
t
5
t
7
DATA BUS
ADDRESS
ENCODE
UPDATE
LATCH
MODE
CS
RD
D0–D7
MX7576*
VALID
DATA
UPDATING
IMPEDANCE
DEFER
HIGH-
BUS
7