WM8900LGEFK/RV Wolfson Microelectronics, WM8900LGEFK/RV Datasheet - Page 76

• Manufacturer Part Number: WM8900LGEFK/RV
• Description: Audio CODECs Ultra Low Power Hi-Fi CODEC
• Manufacturer: Wolfson Microelectronics

Specifications of WM8900LGEFK/RV

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

WM8900
Figure 46 System Clocking
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The overall clocking scheme is illustrated in Figure 46.
SYSCLK CONTROL
The MCLK_SRC bit is used to select the source for SYSCLK. The source may be either MCLK or
the output of the FLL. These fields are described in Table 56. See “FLL” for further details of the
Frequency Locked Loop control.
When the internal clock source is switched from one value to another using MCLK_SRC, the
change of source will only occur following a falling edge of the source signal that was originally
selected. In the case where the clock source is switched from FLL to MCLK, a suitable falling edge
can be ensured by disabling the FLL after selection of MCLK as the source.
The recommended sequence of actions to switch from FLL to MCLK source is as follows:
Note that, as an alternative to the above sequence, a software reset may be used to re-select
MCLK as the default SYSCLK source
The recommended sequence of actions to switch from MCLK to FLL source is as follows:
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Select MCLK as source (MCLK_SRC = 0)
Disable FLL (FLL_ENA = 0)
Disable FLL oscillator (FLL_OSC_ENA = 0) (Optional)
Enable FLL oscillator (FLL_OSC_ENA = 1)
Enable FLL (FLL_ENA = 1)
Allow for FLL lock time to elapse.
Select FLL as source (MCLK_SRC = 1)
PD, August 2008, Rev 4.0
Production Data
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