WM8903LGEFK/RV Wolfson Microelectronics, WM8903LGEFK/RV Datasheet - Page 98

• Manufacturer Part Number: WM8903LGEFK/RV
• Description: Audio CODECs ULTRA LOW PWR HI FI CODEC
• Manufacturer: Wolfson Microelectronics

Specifications of WM8903LGEFK/RV

• Audio Codec Type: Stereo Codec
• No. Of Adcs: 2
• No. Of Dacs: 2
• No. Of Input Channels: 6
• No. Of Output Channels: 8
• Adc / Dac Resolution: 24bit
• Sampling Rate: 96kHz
• Operating Temperature Range: -40°C To +85°C
• Rohs Compliant: Yes
• Adcs / Dacs Signal To Noise Ratio: 96dB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

WM8903
CONTROL INTERFACE
w
Table 66 Interrupt Control
The WM8903 is controlled by writing to registers through a 2-wire serial control interface. A control
word consists of 24 bits, transmitted as 3 bytes. The first byte (bits B23 to B16) is a register address
that select which control register is accessed. The remaining two bytes (bits B15 to B0) are data,
corresponding to the 16 bits in each control register.
In order to allow many devices to share a single 2-wire control bus, every device on the bus has a
unique 7-bit device ID (this is not the same as the 8-bit address of each register in the WM8903).
The default device ID for the WM8903 is 0011010 (0x34h). Alternatively, the device ID can be set to
0011011 (0x36) by pulling the GPIO3/ADDR pin high during device start-up, when the internal power-
on reset signal PORB (see “Power-on Reset”) is released. The setup and hold times for device ID
selection are shown in Table 67. After the device ID has been selected, the GPIO3/ADDR pin can be
used as a GPIO.
Table 67 GPIO3/ADDR Latch on Power-up Timing
The WM8903 operates as a slave device only. The controller indicates the start of data transfer with
a high to low transition on SDIN while SCLK remains high. This indicates that a device ID, register
address and data will follow. All devices on the 2-wire bus respond to the start condition and shift in
the next eight bits on SDIN (7-bit device ID + Read/Write bit, MSB first). If the device ID received
matches the device ID of the WM8903, then the WM8903 responds by pulling SDIN low on the next
clock pulse (ACK). If the device ID is not recognised or the R/W bit is ‘1’ when operating in write only
mode, the WM8903 returns to the idle condition and waits for a new start condition and valid
address.
Register map access is possible with or without a Master Clock (MCLK). However, if CLK_SYS_ENA
has been set to 1, then a Master Clock must be present for control register Read/Write operations. If
CLK_SYS_ENA = 1 and MCLK is not present, then register access will be unsuccessful.
If it cannot be assured that MCLK is present when accessing the register map, then CLK_SYS_ENA
should be cleared to 0 to ensure correct operation. The register containing CLK_SYS_ENA (R22)
can be accessed even if CLK_SYS_ENA = 1 and MCLK is not present. See also the Control
Interface Clocking “section.
R123 (7Bh)
Interrupt
Polarity 1
R126 (7Eh)
Interrupt
Control
REGISTER
SYMBOL
ADDRESS
T
T
pusetup
puhold
MIN
100
100
BIT
15
14
0
0
TYP
IM_GP1_EINT
MICSHRT_INV
MICDET_INV
IRQ_POL
LABEL
MAX
UNIT
μs
μs
DEFAULT
1
0
0
0
Interrupt mask for GPIO1/DMIC_LR
0 = Not masked
1 = Masked
MICBIAS Short Circuit detect
polarity
0 = Detect current increase above
threshold
1 = Detect current decrease below
threshold
MICBIAS Current Detect polarity
0 = Detect current increase above
threshold
1 = Detect current decrease below
threshold
Interrupt Output polarity
0 = Active high
1 = Active low
PP, Rev 3.1, August 2009
DESCRIPTION
Pre-Production
98