CS4272-DZZR Cirrus Logic Inc, CS4272-DZZR Datasheet - Page 43

• Manufacturer Part Number: CS4272-DZZR
• Description: Audio CODECs IC 24Bit 192kHz 114dB Str Codec
• Manufacturer: Cirrus Logic Inc

Specifications of CS4272-DZZR

• Number Of Adc Inputs: 2
• Number Of Dac Outputs: 2
• Conversion Rate: 192 KSPs
• Interface Type: Serial (I2S, SPI)
• Resolution: 24 bit
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: TSSOP-28
• Minimum Operating Temperature: - 40 C
• Number Of Channels: 2 ADC, 2 DAC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

8.6
8.6.1
8.6.2
8.6.3
8.6.4
8.7
8.7.1
8.7.2
DS593F1
Reserved
Reserved
7
7
ADC Control - Address 06h
Mode Control 2 - Address 07h
Function:
Function:
Function:
Function:
Function:
Function:
ADC_DIF
Dither for 16-Bit Data (Bit 5)
ADC Digital Interface Format (Bit 4)
ADC Channel A & B Mute (Bits 3:2)
Channel A & B High Pass Filter Disable (Bits 1:0)
Digital Loopback (Bit 4)
AMUTEC = BMUTEC (Bit 3)
0
1
When set, this bit activates the Dither for 16-Bit Data feature as described in “Dither for 16-Bit Data”
on page 30.
The required relationship between LRCK, SCLK and SDOUT for the ADC is defined by the ADC Dig-
ital Interface Format. The options are detailed in Table 17 and may be seen in Figure 3 and 4.
When this bit is set, the output of the ADC for the selected channel will be muted.
When this bit is set, the internal high-pass filter for the selected channel will be disabled.The current
DC offset value will be frozen and continue to be subtracted from the conversion result. See “High
Pass Filter and DC Offset Calibration” on page 30.
When this bit is set, an internal digital loopback from the ADC to the DAC will be enabled. Please refer
to “Internal Digital Loopback” on page 30.
When this function is enabled, the individual controls for AMUTEC and BMUTEC are internally con-
nected through an AND gate prior to the output pins. Therefore, the external AMUTEC and BMUTEC
pins will go active only when the requirements for both AMUTEC and BMUTEC are valid.
Reserved
Reserved
6
6
Left Justified, up to 24-bit data (default)
Reserved
Dither16
5
5
Table 17. ADC Digital Interface Formats
I
2
S, up to 24-bit data
Description
ADC_DIF
LOOP
4
4
MUTECA=B
MUTEA
3
3
FREEZE
MUTEB
Format
2
2
0
1
HPFDisableA HPFDisableB
CPEN
1
1
Figure
3
4
CS4272
PDN
0
0
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