SL38000ZCT Silicon Laboratories Inc, SL38000ZCT Datasheet - Page 9

• Manufacturer Part Number: SL38000ZCT
• Description: Clock Generators & Support Products 1-200MHz 4PLL 9Out CG/SSCG 3.3-2.5V
• Manufacturer: Silicon Laboratories Inc

Specifications of SL38000ZCT

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

SDATA
SCLK
SDA/SCLK
fall time
STOP set-up
time
Bus free time
External Components & Design Considerations
Typical Application Schematic
TBD
Rev 1.1, August 7, 2008
t
Comments and Recommendations
Decoupling Capacitor: A decoupling capacitor of 0.1μF must be used between all VDD and VSS pins on PCB.
Place the capacitor on the component side of the PCB as close to the VDD pins as possible. The PCB trace to the
VDD pins and to the GND via should be kept as short as possible Do not use vias between the decoupling capacitor
and the VDD pins.
Series Termination Resistor: A series termination resistor is recommended if the distance between the outputs
(CLKOUT or REFCLK pins) and the load is over 1 ½ inch. The nominal impedance of the all clock outputs are about
25 Ω. Use 20 Ω resistor in series with the output to terminate 50Ω trace impedance and place 20 Ω resistor as close
to the SSCLK output as possible.
Crystal and Crystal Load: Use only parallel resonant fundamental crystals. DO NOT USE higher overtone crystals.
To meet the crystal initial accuracy specification (in ppm); the internal on-chip programmable capacitors PCin and
PCout must be programmed to match the crystal load requirement. These values are given by the formula below:
F
S
t
HD;STA
t
LOW
t
SU;STO
t
BUF
t
F
t
R
t
HD;DAT
Table 2. I2C-Bus Timing Specification
t
SU;DAT
t
4.0
4.7
HIGH
-
I2C-Bus Timing Diagram
t
F
t
SU;STA
300
-
-
Sr
0.6
1.3
t
-
HD;STA
300
-
-
t
SU;STO
SL38000
t
R
Page 9 of 12
P
ns
ns
μs
t
BUF
S