SL28610BLCT Silicon Laboratories Inc, SL28610BLCT Datasheet - Page 3

• Manufacturer Part Number: SL28610BLCT
• Description: Clock Generators & Support Products AtomPoulsbo Handheld Embed.1.5V PCIe G1
• Manufacturer: Silicon Laboratories Inc

Specifications of SL28610BLCT

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Pin Definitions
Table 1. Frequency Select Pin (FSB and FSC)
Frequency Select Pin (FSB and FSC)
Apply the appropriate logic levels to FSB and FSC inputs
before CKPWRGD assertion to achieve host clock frequency
selection. When the clock chip sampled LOW on CKPWRGD
and indicates that VTT voltage is stable then FSB and FSC
input values are sampled. This process employs a one-shot
functionality and once the CKPWRGD sampled a valid LOW,
all other FSB, FSC, and CKPWRGD transitions are ignored
except in test mode.
Serial Data Interface
To enhance the flexibility and function of the clock synthesizer,
a two-signal serial interface is provided. Through the Serial
Data Interface, various device functions, such as individual
clock output buffers are individually enabled or disabled. The
registers associated with the Serial Data Interface initialize to
their default setting at power-up. The use of this interface is
.
Table 2. Command Code Definition
Table 3. Block Read and Block Write Protocol
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40
41
42
43
44
45
46
47
48
Pin No.
(6:0)
FSC
Bit
18:11
7
Bit
8:2
1
0
0
1
10
19
1
9
VSS
VDD1.5_IO
VDD1.5_CORE
CPU1#
CPU1
VSS_CPU
VDD1.5_IO
CPU2#
CPU2
0 = Block read or block write operation, 1 = Byte read or byte write operation
Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be '0000000'
Start
Slave address–7 bits
Write
Acknowledge from slave
Command Code–8 bits
Acknowledge from slave
FSB
0
0
1
1
Name
(continued)
Block Write Protocol
100 MHz
133 MHz
166 MHz
200 MHz
CPU
Description
O, DIF Complementary Host Differential clock
O, DIF True Host Differential clock
O, DIF Complementary Host Differential clock
O, DIF True Host Differential clock
PWR
PWR
PWR
Type
GND
GND
100 MHz
100 MHz
100 MHz
100 MHz
PCIe
Ground
1.5V Power Supply for differential output
1.5V Power Supply for core
Ground
1.5V Power Supply for differential output
100 MHz
100 MHz
100 MHz
100 MHz
LCD
Description
optional. Clock device register changes are normally made at
system initialization, if any are required. The interface cannot
be used during system operation for power management
functions.
Data Protocol
The clock driver serial protocol accepts byte write, byte read,
block write, and block read operations from the controller. For
block write/read operation, access the bytes in sequential
order from lowest to highest (most significant bit first) with the
ability to stop after any complete byte is transferred. For byte
write and byte read operations, the system controller can
access individually indexed bytes. The offset of the indexed
byte is encoded in the command code described in Table 2.
The block write and block read protocol is outlined in Table 3
while Table 4 outlines byte write and byte read protocol. The
slave receiver address is 11010010 (D2h).
18:11
8:2
Bit
10
19
1
9
96 MHz
96 MHz
96 MHz
96 MHz
DOT96
Start
Slave address–7 bits
Write
Acknowledge from slave
Command Code–8 bits
Acknowledge from slave
Description
14.318 MHz
14.318 MHz
14.318 MHz
14.318 MHz
Block Read Protocol
REF
Description
SL28610