MC100LVE222FAR2 ON Semiconductor, MC100LVE222FAR2 Datasheet - Page 5

• Manufacturer Part Number: MC100LVE222FAR2
• Description: Clock Drivers & Distribution 3.3V 1:15 Diff ECL
• Manufacturer: ON Semiconductor
• Type: ECL, PECLr

Specifications of MC100LVE222FAR2

• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Multiply / Divide Factor: 2:1
• Number Of Clock Inputs: 2
• Output Logic Level: ECL
• Supply Voltage (max): +/- 5.25 V
• Supply Voltage (min): +/- 3 V
• Maximum Operating Temperature: + 85 C
• Package / Case: LQFP-52
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
7. V
8. The differential propagation delay is defined as the delay from the crossing points of the differential input signals to the crossing point of the
9. The single‐ended propagation delay is defined as the delay from the 50% point of the input signal to the 50% point of the output signal.
10. The within-device skew is defined as the worst case difference between any two similar delay paths within a single device.
11. V
Table 6. AC CHARACTERISTICS
Symbol
f
t
t
t
t
V
t
max
PLH
PHL
skew
JITTER
r
/t
PP
differential output signals.
for the LVE222. A differential input as low as 50 mV will still produce full ECL levels at the output.
f
EE
PP
(min) is defined as the minimum input differential voltage which will cause no increase in the propagation delay. The V
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
can vary +0.3 V to -1.95 V. Operation with |V
Maximum Toggle Frequency
Propagation Delay to Output
Within-Device Skew (Note 10)
Part-to-Part Skew
(Differential Configuration)
Random CLOCK Jitter (RMS)
Input Swing (Differential) (Note 11)
Output Rise/Fall Time 20%-80%
IN (single-ended) (Note 9)
Characteristic
IN (differential) (Note 8)
(Refer to Application Note AND8020 - Termination of ECL Logic Devices)
Figure 4. Typical Termination for Output Driver and Device Evaluation
Driver
Device
V
CC
Q
Q
or V
MR
CCO
1040
1100
Min
940
400
200
CC
1.2
= 3.3 V; V
or pV
http://onsemi.com
MC100LVE222
-40°C
Z = 50 W
Z = 50 W
> 1.5
1140
1140
1250
< 1.0
CCO
Typ
V
EE
TT
-V
= 0.0 V or V
= (V
50
EE
5
1240
1290
1400
| w3.8 V span will require special thermal handling considerations.
Max
1000
CC
200
600
W
50
or V
V TT
CC
CCO
1080
1170
Min
980
400
200
1.2
/V
50
) - 2.0 V
CCO
W
= 0.0 V; V
25°C
> 1.5
1320
< 1.0
1180
1180
Typ
D
D
EE
1280
1330
1470
1000
Max
200
600
50
= -3.3 V (Note 7)
Receiver
Device
1020
1220
1120
Min
400
200
1.2
70°C
> 1.5
1220
1220
1370
< 1.0
Typ
PP
(min) is AC limited
1320
1370
1520
1000
Max
200
600
50
GHz
Unit
mV
ps
ps
ps
ps