CY2PP3220AI Cypress Semiconductor Corp, CY2PP3220AI Datasheet

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CY2PP3220AI

Manufacturer Part Number
CY2PP3220AI
Description
Clock Buffer 2.5V or 3.3V 1.5GHz IND
Manufacturer
Cypress Semiconductor Corp
Datasheet

Specifications of CY2PP3220AI

Number Of Outputs
40
Max Input Freq
1500 MHz
Propagation Delay (max)
0.75 ns
Supply Voltage (max)
+/- 3.465 V
Supply Voltage (min)
+/- 2.375 V
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Package / Case
TQFP-52
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CY2PP3220AI
Manufacturer:
CY
Quantity:
51
Cypress Semiconductor Corporation
Document #: 38-07513 Rev.*C
Features
• Two sets of ten ECL/PECL differential outputs
• Two ECL/PECL differential inputs
• Hot-swappable/-insertable
• 50 ps output-to-output skew
• 150 ps device-to-device skew
• 500 ps propagation delay (typical)
• 1.5 GHz Operation (2.7 GHz max. toggle frequency)
• PECL mode supply range: V
• ECL mode supply range: V
• Industrial temperature range: –40°C to 85°C
• 52-pin 1.4-mm TQFP package
• Temperature compensation like 100K ECL
• Pin compatible with MC100ES6220
Block Diagram
with V
with V
EE
CC
CLKA#
CLKB#
CLKB
CLKA
= 0V
= 0V
V
V
V
V
EE
CC
EE
CC
V
V
EE
EE
E E
Dual 1:10 Differential Clock/Data Fanout Buffer
CC
= –2.5V± 5% to –3.3V±5%
= 2.5V± 5% to 3.3V±5%
3901 North First Street
QA0
QA0#
QA9
QA9#
QB0
QB0#
QB9
QB9#
VBB
Functional Description
The CY2PP3220 is a low-skew, low propagation delay dual
1-to-10 differential fanout buffer targeted to meet the require-
ments of high-performance clock and data distribution applica-
tions. The device is implemented on SiGe technology and has
a fully differential internal architecture that is optimized to
achieve low signal skews at operating frequencies of up to 1.5
GHz.
The device features two differential input paths that are differ-
ential internally. The CY2PP3220 may function not only as a
differential clock buffer but also as a signal-level translator and
fanout on ECL/PECL signal to twenty ECL/PECL differential
loads. An external bias pin, VBB, is provided for this purpose.
In such an application, the VBB pin should be connected to
either one of the CLKA# or CLKB# inputs and bypassed to
ground via a 0.01-PF capacitor. Traditionally, in ECL, it is used
to provide the reference level to a receiving single-ended input
that might have a different self-bias point.
Since the CY2PP3220 introduces negligible jitter to the timing
budget, it is the ideal choice for distributing high frequency,
high precision clocks across back-planes and boards in com-
munication systems. Furthermore, advanced circuit design
schemes, such as internal temperature compensation, ensure
that the CY2PP3220 delivers consistent performance over
various platforms.
CLKA#
CLKB#
CLKA
CLKB
QB9#
QB8#
VCC
VCC
VBB
QB9
QB8
VEE
VEE
Pin Configuration
52
10
12
11
13
San Jose
4
5
6
7
8
9
1
2
3
14
51
15
50
16
49
17
CY2PP3220
48
,
18
CA 95134
47
19
46
20
FastEdge™ Series
45
21
44
22
43
23
Revised July 28, 2004
42
24
41
25
CY2PP3220
40
26
30
39
38
37
36
35
34
33
32
31
29
28
27
408-943-2600
QA6
QA6#
QA7
QA7#
QA8
QA8#
QA9
QA9#
QB0
QB0#
QB1
QB1#
VCC

Related parts for CY2PP3220AI

CY2PP3220AI Summary of contents

Page 1

... CLKB CLKB Cypress Semiconductor Corporation Document #: 38-07513 Rev.*C Functional Description The CY2PP3220 is a low-skew, low propagation delay dual 1-to-10 differential fanout buffer targeted to meet the require- ments of high-performance clock and data distribution applica- tions. The device is implemented on SiGe technology and has a fully differential internal architecture that is optimized to achieve low signal skews at operating frequencies ...

Page 2

Pin Definitions Pin Name 4 CLKA, 5 CLKA# [3] 6 VBB 7 CLKB, 8 CLKB# [2] 3,9 VEE 1,2,14,27,40 VCC 52,50,48,46,44,42,39,37, QA(0:9) 35,33 51,49,47,45,43,41,38,36, QA#(0:9) 34,32 31,29,26,24,22,20,18,16, QB(0:9) 13,11 30,28,25,23,21,19,17,15, QB#(0:9) 12,10 Governing Agencies The following agencies ...

Page 3

Absolute Maximum Ratings Parameter Description V Positive Supply Voltage CC V Negative Supply Voltage EE T Temperature, Storage S T Temperature, Junction J ESD ESD Protection h M Moisture Sensitivity Level SL Gate Count Total Number of Used Gates Multiple ...

Page 4

ECL DC Electrical Specifications Parameter Description V Negative Power Supply EE V Differential cross point voltage CMR V Output High Voltage OH V Output Low Voltage –3.3V ± –2.5V ± ...

Page 5

...

Page 6

Applications Information Termination Examples Figure 5. Standard LVPECL – PECL Output Termination Figure ...

Page 7

... Figure 8. Termination for LVPECL to HTSL interface for VCC=2.5V would use X=50 Ohms, Y=2300 Ohms, and Z=1000 Ohms. See application note titled, “PECL Translation, SAW Oscillators, and Specs” for other signalling standards and Ordering Information Part Number CY2PP3220AI CY2PP3220AIT Document #: 38-07513 Rev.*C VDD-2 VCC X ...

Page 8

... Document #: 38-07513 Rev.*C © Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress ...

Page 9

Document History Page Document Title: CY2PP3220 FastEdge™ Series Dual 1:10 Differential Clock/Data Fanout Buffer Document Number: 38-07513 REV. ECN NO. Issue Date ** 122437 02/13/03 *A 125459 04/16/03 *B 229372 See ECN *C 247613 See ECN Document #: 38-07513 Rev.*C ...

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