ETHER-1GQD-O4-B1 Lattice, ETHER-1GQD-O4-B1 Datasheet - Page 7

• Manufacturer Part Number: ETHER-1GQD-O4-B1
• Description: Ethernet ICs Quad Gigabit Ethernet
• Manufacturer: Lattice

Specifications of ETHER-1GQD-O4-B1

• Product: Ethernet Controllers
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Table 1. Tri-Speed Ethernet MAC Input and Output Signals (Continued)
Parameter Descriptions
The Tri-Speed MAC includes configurable parameters to allow easy integration with the user’s application. The con-
figurable parameters are shown in Table 2.
Table 2. Tri-Speed MAC Configuration Parameters
Functional Description
The Tri-Speed MAC is a fully synchronous machine composed of Transmit and Receive MAC sections that operate
independently to support full duplex operation.
The block diagram of the Tri-Speed MAC core is shown in Figure 2. The major functional modules are:
• Host Interface
• Receive MAC
• Transmit MAC
• Internal Buffers and FIFO Interfaces
• G/MII
• (Optional) Management Interface Module
In the Gigabit mode, the 62.5 MHz system clock is supplied to the Transmit MAC. The system clock multiplied by
two is used to clock the GMII interface for data transmission. When receiving data, an external PHY device pro-
vides the 125 MHz clock to the GMII receive section. The 125 MHz clock is divided by two and used to clock the
Receive MAC.
In the 10/100 mode, an external PHY device supplies the clock to the Transmit MAC and the Receive MAC.
ignore_next_pkt
rx_eof
rx_error
rx_fifo_error
MODE
MIIM_MODULE
CPU_DATA_WIDTH
Parameter
Port Name
Include, or Do Not
1000 Mbps Mode,
8 bits, or 16 bits
or 10/100 Mbps
Value Range
Include
Mode
Output
Output
Output
Type
Input
1000 Mbps
Default
Include
16 bits
Mode
Active
State
High
High
High
High
This parameter defines the Ethernet speed the core will support. The
terms “1000 Mbps Mode” and “Gigabit Mode” are used interchange-
ably in this document. “10/100 Mbps Mode” and “Fast Mode” are also
used interchangeably.
This parameter determines whether or not the optional MIIM Module
will be included in the core’s implementation.
This parameter determines the data bus width that will be used to com-
municate with the host.
Ignore Next Packet. This signal is asserted by the host to prevent
a Receive FIFO Full condition. The Receive MAC continues drop-
ping packets as long as this signal is asserted. This is an asynchro-
nous signal.
End Of Frame. Indicates all the data for the current packet has
passed on to the FIFO.
Receive Packet Error. When asserted, this signal indicates the
packet contains error(s). This signal is qualified with the rx_eof
signal.
Receive FIFO Error. This signal is asserted when the
rx_fifo_full signal was detected asserted during a FIFO write.
It is qualified by rx_eof.
7
Media Access Controller User’s Guide
Description
Description
10/100 and 1Gig Ethernet