LAN9303I-ABZJ SMSC, LAN9303I-ABZJ Datasheet - Page 42

• Manufacturer Part Number: LAN9303I-ABZJ
• Description: Ethernet ICs 3 Port 0/100 Ether Switch MII/RMII/Turb
• Manufacturer: SMSC

Specifications of LAN9303I-ABZJ

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 4 Clocking, Resets, and Power Management
Revision 1.4 (07-07-10)
4.1
4.2
The device includes a clock module which provides generation of all system clocks as required by the
various sub-modules of the device. The device requires a fixed-frequency 25MHz clock source for use
by the internal clock oscillator and PLL. This is typically provided by attaching a 25MHz crystal to the
XI and XO pins as specified in
be provided by driving the XI input pin with a single-ended 25MHz clock source. If a single-ended
source is selected, the clock input must run continuously for normal device operation. The internal PLL
generates a fixed 200MHz base clock which is used to derive all sub-system clocks.
In addition to the sub-system clocks, the clock module is also responsible for generating the clocks
used for the general purpose timer and free-running clock. Refer to
Timer & Free-Running Clock," on page 131
Note: Crystal specifications are provided in
The device provides multiple hardware and software reset sources, which allow varying levels of the
chip to be reset. All resets can be categorized into three reset types as described in the following
sections:
The device supports the use of configuration straps to allow automatic custom configurations of various
parameters. These configuration strap values are set upon de-assertion of all chip-level resets and can
be used to easily set the default parameters of the chip at power-on or pin (nRST) reset. Refer to
Section 4.2.4, "Configuration Straps," on page 45
Note: The EEPROM Loader is run upon a power-on reset, nRST pin reset, and digital reset. Refer
Table 4.1
sections for detailed information on each of these reset types.
Clocks
Resets
—Power-On Reset (POR)
—nRST Pin Reset
—Digital Reset (DIGITAL_RST)
—Port 2 PHY Reset
—Port 1 PHY Reset
—Virtual PHY Reset
Chip-Level Resets
Multi-Module Resets
Single-Module Resets
to
summarizes the effect of the various reset sources on the device. Refer to the following
Section 8.4, "EEPROM Loader," on page 113
Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII
Section 14.6, "Clock Circuit," on page
DATASHEET
42
for additional details.
Table 14.20, “Crystal Specifications,” on page
for detailed information on the usage of these straps.
for additional information.
Chapter 11, "General Purpose
364. Optionally, this clock can
SMSC LAN9303/LAN9303i
364.
Datasheet