LAN9221I-ABZJ SMSC, LAN9221I-ABZJ Datasheet - Page 3

• Manufacturer Part Number: LAN9221I-ABZJ
• Description: Ethernet ICs 16bit High 10/100 Ethernet Controller
• Manufacturer: SMSC
• Type: Single Chip MAC and PHY Controllerr

Specifications of LAN9221I-ABZJ

• Ethernet Connection Type: 10 Base-T, 100 Base-TX
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Product: Ethernet Controllers
• Number Of Transceivers: 1
• Standard Supported: 802.3, 802.3u
• Data Rate: 10 Mbps, 100 Mbps
• Supply Voltage (max): 3.3 V
• Supply Voltage (min): 1.8 V
• Maximum Operating Temperature: + 85 C
• Package / Case: TQFP-100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

High-Performance 16-bit Non-PCI 10/100 Ethernet Controller with Variable Voltage I/O
General Description
SMSC LAN9221/LAN9221i
The LAN9221/LAN9221i is a full-featured, single-chip 10/100 Ethernet controller designed for
embedded applications where performance, flexibility, ease of integration and system cost control are
required. The LAN9221/LAN9221i has been specifically designed to provide high performance and
throughput for 16-bit applications. The LAN9221/LAN9221i is fully IEEE 802.3 10BASE-T and 802.3u
100BASE-TX compliant, and supports HP Auto-MDIX. The variable voltage I/O signals of the
LAN9221/LAN9221i accommodate lower voltage I/O signalling without the need for voltage level
shifters.
The LAN9221/LAN9221i includes an integrated Ethernet MAC and PHY with a high-performance
SRAM-like slave interface. The simple, yet highly functional host bus interface provides a glue-less
connection to most common 16-bit microprocessors and microcontrollers as well as 32-bit
microprocessors with a 16-bit external bus. The integrated checksum offload engines enable the
automatic generation of the 16-bit checksum for received and transmitted Ethernet frames, offloading
the task from the CPU. The LAN9221/LAN9221i also includes large transmit and receive data FIFOs
to accommodate high latency applications. In addition, the LAN9221/LAN9221i memory buffer
architecture allows highly efficient use of memory resources by optimizing packet granularity.
Applications
The LAN9221/LAN9221i is well suited for many high-performance embedded applications, including:
The LAN9221/LAN9221i also supports features which reduce or eliminate packet loss. Its internal 16-
KByte SRAM can hold over 200 received packets. If the receive FIFO gets too full, the
LAN9221/LAN9221i can automatically generate flow control packets to the remote node, or assert
back-pressure on the remote node by generating network collisions.
The LAN9221/LAN9221i supports numerous power management and wakeup features. The
LAN9221/LAN9221i can be placed in a reduced power mode and can be programmed to issue an
external wake signal via several methods, including “Magic Packet”, “Wake on LAN” and “Link Status
Change”. This signal is ideal for triggering system power-up using remote Ethernet wakeup events.
The device can be removed from the low power state via a host processor command.
Cable, satellite and IP set-top boxes
High-end audio distribution systems
Digital video recorders
DVD Recorders/Players
Digital TV
Digital media clients/servers
Home gateways
Industrial and embedded systems with extended temperature support
PRODUCT PREVIEW
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Revision 2.7 (03-15-10)